US5155700A
Expired / Lapsed
US
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Method for reducing coupling noise of word lines in a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-02-28
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Granted: 1992-10-13
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Expires: 2010-02-28
Abstract
Abstract The higher packing cells memory circuit includes a plurality word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers by, for example, arranging word lines in a group to provide a cross-over or to twist the word line is not continuously adjacent to the same neighboring word line, so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.
Inventors
- 👤 Dong-Sun Min
- 👤 Su-In Cho
- 👤 Dae-Je Jin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/06; G11C5/063; G11C8/00; G11C8/14; H10W20/41; H10W20/423
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
86 words
In a semiconductor memory device having a plurality of word lines, said semiconductor memory device characterized in that said word lines are divided into several groups, wherein each group has at least four word lines, and wherein said word lines remain in a respective one of said groups, said word lines being disposed to cross each other at a predetermined location so that each word line is not continuously adjacent to any of its neighboring word lines, said predetermined location being the same for each group.
Claim 2
Dependent Claim
86 words
In a semiconductor memory device having a plurality of word lines, said semiconductor memory device characterized in that said word lines are divided into several groups, wherein each group has at least four word lines, and wherein said word lines remain in a respective one of said groups, said word lines being disposed to cross each other at a predetermined location so that each word line is not continuously adjacent to any of its neighboring word lines, said predetermined location being the same for each group.
Claim 3
Dependent Claim
24 words
The semiconductor memory device of claim 1, wherein said word lines are disposed to cross in a strapping area of said semiconductor memory device.
Claim 4
Dependent Claim
46 words
The semiconductor memory device of claim 1, wherein said lines are disposed to cross in more than two locations of said semiconductor memory device so that each word line is not continuously adjacent to said neighboring word lines, said locations being the same for each group.
Claim 5
Dependent Claim
124 words
A semiconductor memory array comprising: a plurality of pairs of bit lines; and a plurality of groups of word lines; said semiconductor memory array characterized in that said plurality of pairs of bit lines do not cross and remain adjacent to each other; said semiconductor memory array characterized further in that each group of said plurality of groups of word lines has at least four word lines, at least four word lines in each group being twisted across each other in a strapping area of said semiconductor memory array so that each of at least four word lines is not continuously adjacent to any neighboring word line, wherein at least four word lines remain in a respective one of said groups of word lines.
Claim 6
Dependent Claim
124 words
A semiconductor memory array comprising: a plurality of pairs of bit lines; and a plurality of groups of word lines; said semiconductor memory array characterized in that said plurality of pairs of bit lines do not cross and remain adjacent to each other; said semiconductor memory array characterized further in that each group of said plurality of groups of word lines has at least four word lines, at least four word lines in each group being twisted across each other in a strapping area of said semiconductor memory array so that each of at least four word lines is not continuously adjacent to any neighboring word line, wherein at least four word lines remain in a respective one of said groups of word lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |