US5241602A
Expired / Lapsed
US
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Parallel scrambling system
Assignee: LG Electronics Inc
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Filing: 1992-05-22
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Granted: 1993-08-31
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Expires: 2012-05-22
Abstract
Abstract A parallel scrambling system comprises an M-bit (M>1) interleaved parallel scrambler for parallel scrambling input signals and an M-bit interleaved multiplexer for multiplexing output signals from the M-bit interleaved parallel scrambler. With this arrangement, an M-bit interleaved parallel scrambling of input signals is carried out prior to a multiplexing thereof. The parallel scrambling system also comprises an M-bit interleaved demultiplexer for receiving a parallel scrambled and multiplexed signal from the M-bit interleaved multiplexer and demultiplexing it and an M-bit interleaved parallel descrambler for descrambling output signals from the demultiplexer to make original signals recover. As the scrambling of input signals is carried out prior to the multiplexing thereof, the scrambler can be operated at the rate identical to the transmission rate of input signals, thereby reducing the manufacture cost and electric power consumption to a minimum.
Inventors
- 👤 Byeong Gi Lee
- 👤 Seok Chang Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:02
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H04K; H04K1/00; H04K1/04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03866; H04L25/03872; H04J2203/00; H04J2203/0001; H04J2203/0089
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
A parallel scrambling system comprising: an M-bit interleaved parallel scrambler for M-bit (M>1) interleaved parallel scrambling n (n>1) input signals and including a first parallel signal generator for generating n (n>1) parallel signals and a first exclusive OR gate circuit having n (n>1) exclusive OR gates for exclusive-ORing said parallel signals from the first parallel signal generator and said input signals, respectively; an M-bit interleaved multiplexer for receiving output signals from said M-bit interleaved parallel scrambler and multiplexing them in the unit of M bits, to output a multiplexed signal; an M-bit interleaved demultiplexer for receiving said multiplexed signal from said M-bit interleaved multiplexer and demultiplexing it in the unit of M bits, to output n (n>1) demultiplexed signals; and an M-bit interleaved parallel descrambler for M-bit interleaved parallel descrambling said demultiplexed signals from said M-bit interleaved demultiplexer to make original signals recover and including a second parallel signal generator having the same construction as that of the first parallel signal generator and generating n (n>1) parallel signals and a second exclusive OR gate circuit having n (n>1) exclusive OR gates for exclusive-ORing said parallel signals from the second parallel signal generator and the demultiplexed signals, respectively.
Claim 2
Dependent Claim
197 words
A parallel scrambling system comprising: an M-bit interleaved parallel scrambler for M-bit (M>1) interleaved parallel scrambling n (n>1) input signals and including a first parallel signal generator for generating n (n>1) parallel signals and a first exclusive OR gate circuit having n (n>1) exclusive OR gates for exclusive-ORing said parallel signals from the first parallel signal generator and said input signals, respectively; an M-bit interleaved multiplexer for receiving output signals from said M-bit interleaved parallel scrambler and multiplexing them in the unit of M bits, to output a multiplexed signal; an M-bit interleaved demultiplexer for receiving said multiplexed signal from said M-bit interleaved multiplexer and demultiplexing it in the unit of M bits, to output n (n>1) demultiplexed signals; and an M-bit interleaved parallel descrambler for M-bit interleaved parallel descrambling said demultiplexed signals from said M-bit interleaved demultiplexer to make original signals recover and including a second parallel signal generator having the same construction as that of the first parallel signal generator and generating n (n>1) parallel signals and a second exclusive OR gate circuit having n (n>1) exclusive OR gates for exclusive-ORing said parallel signals from the second parallel signal generator and the demultiplexed signals, respectively.
Claim 3
Dependent Claim
115 words
A parallel scrambling system in accordance with claim 1, wherein in case that said M-bit interleaved parallel scrambler has a characteristic polynomial with the degree of n (n>1), said first parallel signal generator comprises first to n-th shift register groups each including M (M>1) shift registers sequentially connected with one another and means for continuously exclusive-ORing outputs from respective final shift registers of shift register groups corresponding respectively to exponents (k) (1≦K≦n) of items (x R ) in said characteristic polynomial, among said n shift register groups, then outputting the ORed results to the first shift register of the first shift register group, said means sequentially connecting all the shift register groups with one another.
Claim 4
Dependent Claim
59 words
A parallel scrambling system in accordance with claim 2, wherein said first parallel signal generator further comprises means for causing the first parallel signal among said n parallel signals to be generated by the final shift register of the n-th shift register group and causing the remaining parallel signals to be generated by exclusive-ORing outputs from predetermined shift registers.
Claim 5
Dependent Claim
162 words
A parallel scrambling system in accordance with claim 1, wherein in case that said M-bit interleaved parallel scrambler has a characteristic polynomial with the degree of n (n>1), said first parallel signal generator comprises first to n-th shift register groups each including M (M>1) shift registers sequentially connected with one another and means for outputting an output from the first shift register in the n-th shift register group to the first shift register in the first shift register group, and at the same time, exclusive-ORing said output from the first shift register in the n-th shift register group and respective outputs from final shift registers of shift register groups corresponding respectively to exponents (k) (1≦K≦n) other than n of items (x k ) in said characteristic polynomial, among said n shift register groups, then outputting the ORed results to first shift registers of next higher degree shift register groups, respectively, said means sequentially connecting all the shift register groups with one another.
Claim 6
Dependent Claim
59 words
A parallel scrambling system in accordance with claim 4, wherein said first parallel signal generator further comprises means for causing the first parallel signal among said n parallel signals to be generated by the final shift register of the n-th shift register group and causing the remaining parallel signals to be generated by exclusive-ORing outputs from predetermined shift registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |