US5241506A
Expired / Lapsed
US
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Semiconductor memory circuit apparatus
Assignee: Toshiba Corp
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Filing: 1990-11-14
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Granted: 1993-08-31
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Expires: 2010-11-14
Abstract
Abstract A random access memory (RAM) array has a dummy word line having a similar pattern to the word lines provided for the RAM cells. A transistor having the same channel width and channel length as one of the transistors in the RAM cells has its gate connected to the dummy word line. An inverter is formed of three transistors including the transistor having its gate connected to the dummy word line, with the output of the inverter connected to a capacitor. The capacitance of the capacitor is set close to the capacitance of a bus line of the RAM to adjust the dummy word line and the word lines of the RAM circuits to have the same transfer delay. If the capacitance of the capacitor is made slightly smaller than the bus line capacitance, the potential at the output of the inverter can be changed by this difference. The output of the inverter is detected, and can be used as a drive signal to drive a sense amplifier used to read the RAM cells. Further, the signal traveling through the dummy word line can be used as a precharge signal.
Inventors
- 👤 Hiroyuki Motegi
- 👤 Hideaki Uchida
- 👤 Yasunori Kuwashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:19
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
254 words
A semiconductor memory circuit apparatus, comprising: a random access memory having memory cells arranged in a matrix connected to a plurality of word lines and bus lines, each of the memory cells including a load element, a first transistor connected to the load element at a first node, and a second transistor having a source and drain path connected between the first node and the corresponding bus line, and a gate connected to the corresponding word line, wherein each bus line has an associated first capacitor; a sense amplifier for performing a read operation of the random access memory; a third transistor having the same channel length and channel width as the second transistor and having a gate; a dummy word line like one of word lines of the random access memory, the dummy word line being connected to the gate of the third transistor; an inverter having an output terminal and comprising the third transistor and a fourth transistor, having the same channel width and channel length as the first transistor, connected in series between the output terminal and a first voltage supply, and a second load element like the first load element connected between the output terminal and a second voltage supply; wherein the fourth transistor receives an enable signal as a gate input to enable a memory operation; and a second capacitor connected to the output terminal of said inverter at a second node; wherein the potential at the second node is used as a timing signal for the sense amplifier.
Claim 2
Dependent Claim
254 words
A semiconductor memory circuit apparatus, comprising: a random access memory having memory cells arranged in a matrix connected to a plurality of word lines and bus lines, each of the memory cells including a load element, a first transistor connected to the load element at a first node, and a second transistor having a source and drain path connected between the first node and the corresponding bus line, and a gate connected to the corresponding word line, wherein each bus line has an associated first capacitor; a sense amplifier for performing a read operation of the random access memory; a third transistor having the same channel length and channel width as the second transistor and having a gate; a dummy word line like one of word lines of the random access memory, the dummy word line being connected to the gate of the third transistor; an inverter having an output terminal and comprising the third transistor and a fourth transistor, having the same channel width and channel length as the first transistor, connected in series between the output terminal and a first voltage supply, and a second load element like the first load element connected between the output terminal and a second voltage supply; wherein the fourth transistor receives an enable signal as a gate input to enable a memory operation; and a second capacitor connected to the output terminal of said inverter at a second node; wherein the potential at the second node is used as a timing signal for the sense amplifier.
Claim 3
Dependent Claim
211 words
A semiconductor memory circuit apparatus, comprising: a random access memory having a plurality of memory cells arranged in a matrix connected to a plurality of word lines and bus lines, each of said memory cells including a first load element, a first transistor connected to the first load element at a node, and a second transistor having a source and drain path connected between the node and the corresponding bus line, and a gate connected to the corresponding word line, wherein each bus line has an associated first capacitor; a sense amplifier for performing a read operation of the random access memory; a signal generating circuit for precharging the bus lines of the random access memory after one of a read operation and a write operation is performed; a dummy word line longer than one of the word lines of the random access memory like the one word line; a third transistor having the same channel width and channel length as the second transistor, a gate of the third transistor being connected to the dummy word line; a detecting circuit for detecting that the dummy word line becomes unselected; and precharging means for precharging said bus lines of said random access memory in accordance with an output of said detecting circuit.
Claim 4
Dependent Claim
211 words
A semiconductor memory circuit apparatus, comprising: a random access memory having a plurality of memory cells arranged in a matrix connected to a plurality of word lines and bus lines, each of said memory cells including a first load element, a first transistor connected to the first load element at a node, and a second transistor having a source and drain path connected between the node and the corresponding bus line, and a gate connected to the corresponding word line, wherein each bus line has an associated first capacitor; a sense amplifier for performing a read operation of the random access memory; a signal generating circuit for precharging the bus lines of the random access memory after one of a read operation and a write operation is performed; a dummy word line longer than one of the word lines of the random access memory like the one word line; a third transistor having the same channel width and channel length as the second transistor, a gate of the third transistor being connected to the dummy word line; a detecting circuit for detecting that the dummy word line becomes unselected; and precharging means for precharging said bus lines of said random access memory in accordance with an output of said detecting circuit.
Claim 5
Dependent Claim
65 words
An apparatus according to claim 1, further comprising a detecting means for detecting the potential at the second node wherein the second capacitor is used to adjust a time period from a point when the dummy word line starts either charging or discharging to a point when a potential change of said drain is detected, and said sense amplifier is operated by said detecting means.
Claim 6
Independent Claim
23 words
An apparatus according to claims 1 or 3, wherein the second capacitor has a capacitance substantially equal to that of the first capacitor.
Claim 7
Dependent Claim
19 words
An apparatus according to claim 4, wherein the first capacitor is a parasitic capacitor of the associated bus line.
Claim 8
Dependent Claim
72 words
An apparatus according to claim 1, wherein said first and second load elements are a fifth and sixth transistors of a first channel conductivity-type, said first to fourth transistors are a second channel conductivity-type, the channel width and the channel length of the first and the fourth transistors are equal to each other, and the channel length and channel width of the fifth and the sixth transistors are equal to each other.
Claim 9
Independent Claim
133 words
An apparatus according to claims 1, 2 or 3, wherein each of said memory cells further includes a circuit having the same pattern as the combination of the first and second transistors and the first load element, wherein the first transistors and the first load element of the first circuit constitute a first CMOS inverter, a transistor and a load element of the second circuit constitute a second CMOS inverter, an input portion of the first CMOS inverter is connected to an output portion of the second CMOS inverter, an input portion of the second CMOS inventor is connected to an output portion of the first MOS inventor, and outputs from the first and second CMOS inventors are connected to corresponding bus lines via the second transistors of the first and second circuits.
Claim 10
Dependent Claim
24 words
An apparatus according to claim 2, wherein the dummy word line has a capacitance equal to or less than that of the first capacitor.
Claim 11
Dependent Claim
19 words
An apparatus according to claim 8, wherein the first capacitor is a parasitic capacitor of the associated bus line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |