Patent US2361995A successfully refreshed from Google Patents.
EP0337433A2
Expired / Lapsed
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Cell array pattern layout of semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1989-04-12
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Granted: —
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Expires: 2009-04-12
Abstract
Abstract A memory cell array (MCA) includes data storing memory cells (MC) which are arranged in a matrix form of m rows × n columns. The data storing memory cells (MC) are selected by means of m word lines (WL) and n bit lines (BL). Dummy capacitance cells (DC) are arranged on the (n+1)th column of the memory cell array (MCA), and are connected to the word lines (WL). The dummy capacitance cells (DC) are each formed of a transistor which has the same construction as a polyfield transistor or the data storing memory cell (MC) and whose source is set in the electrically floating condition. Cells (C) are arranged on the (m+1)th row of the memory cell array (MCA), and are connected to n bit lines (BL). The cells (C) have no influence on the circuit operation. A dummy cell (DMC) is arranged in an intersecting position of the (m+1)th row and the (n+1)th column. A dummy bit line (DBL) is connected to the dummy capacitance cells (DC) and dummy cell (DMC), and a dummy word line (WL) is connected to the cells (C) and dummy cell (DMC).
Inventors
- 👤 Nobuaki C/O Intellectual Property Div. Ohtsuka
- 👤 Sumio C/O Intellectual Property Div. Tanaka
- 👤 Junichi C/O Intellectual Property Div. Miyamoto
- 👤 Shigeru C/O Intellectual Property Div. Atsumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 07:42
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
240 words
A semiconductor memory device for comparing a potential read out from a memory cell (MC) with a potential read out from a dummy cell (DMC) and amplifying a difference between the compared potentials; characterized by comprising a memory cell array (MCA) including data storing memory cells (MC) which are arranged in a form of m rows and n columns; m word lines (WL) arranged along respective rows of said data storing memory cells (MC) for selecting the row of said memory cells (MC); n bit lines (BL) arranged along respective columns of said data storing memory cells (MC) for selecting the column of said memory cells (MC) to permit data transfer; dummy capacitance cells (DC) arranged on a "k"th column of said memory cell array (MCA) and respectively connected to said m word lines (WL), said "k" defining any one number selected from 1 through n+1; cells (C) arranged on an "ℓ"th row of said memory cell array (MCA) and respectively connected to said n bit lines (BL) without having any connection with the circuit operation, said "ℓ" defining any one number selected from 1 through m+1; a dummy cell (DMC) arranged in an intersecting position of the "ℓ"th row and "k"th column of said memory cell array (MCA); a dummy bit line (DBL) connected to said dummy capacitance cell (DC) and dummy cell (DMC); and a dummy word line (DWL) connected to said cells (C) and dummy cell (DMC).
Claim 2
Dependent Claim
240 words
A semiconductor memory device for comparing a potential read out from a memory cell (MC) with a potential read out from a dummy cell (DMC) and amplifying a difference between the compared potentials; characterized by comprising a memory cell array (MCA) including data storing memory cells (MC) which are arranged in a form of m rows and n columns; m word lines (WL) arranged along respective rows of said data storing memory cells (MC) for selecting the row of said memory cells (MC); n bit lines (BL) arranged along respective columns of said data storing memory cells (MC) for selecting the column of said memory cells (MC) to permit data transfer; dummy capacitance cells (DC) arranged on a "k"th column of said memory cell array (MCA) and respectively connected to said m word lines (WL), said "k" defining any one number selected from 1 through n+1; cells (C) arranged on an "ℓ"th row of said memory cell array (MCA) and respectively connected to said n bit lines (BL) without having any connection with the circuit operation, said "ℓ" defining any one number selected from 1 through m+1; a dummy cell (DMC) arranged in an intersecting position of the "ℓ"th row and "k"th column of said memory cell array (MCA); a dummy bit line (DBL) connected to said dummy capacitance cell (DC) and dummy cell (DMC); and a dummy word line (DWL) connected to said cells (C) and dummy cell (DMC).
Claim 3
Dependent Claim
23 words
A semiconductor memory device according to claim 1, characterized in that said memory cells (MC) each include a floating gate type MOS transistor.
Claim 4
Dependent Claim
29 words
A semiconductor memory device according to claim 1, characterized in that said dummy memory cell (DMC) is formed with the same structure as that of said memory cell (MC).
Claim 5
Dependent Claim
22 words
A semiconductor memory device according to claim 3, characterized in that said dummy cell (DMC) includes a floating gate type MOS transistor.
Claim 6
Dependent Claim
25 words
A semiconductor memory device according to claim 1, characterized in that said dummy capacitance cells (DC) serve as loads of said dummy bit line (DBL).
Claim 7
Dependent Claim
21 words
A semiconductor memory device according to claim 1, characterized in that said dummy capacitance cells (DC) each include a polyfield transistor.
Claim 8
Dependent Claim
166 words
A semiconductor memory device according to claim 6, characterized in that said polyfield transistor includes a semiconductor substrate (10) of a first conductivity type; a drain diffusion region (D11) of a second conductivity type formed in the surface area of said semiconductor substrate (10) and connected to said dummy bit line (DBL); a source diffusion region (D12) of the second conductivity type formed separately from said drain diffusion region (D11) in the surface area of said semiconductor substrate (10) and connected to a potential supplying source; a field insulation film (D14) formed on that portion of said semiconductor substrate (10) which lies between said drain diffusion region (D11) and source diffusion region (D12); a first insulation film (D15) formed on said field insulation film (D14); a floating gate (D16) formed on said first insulation film (D15); a second insulation film (D17) formed on said floating gate (D16); and a control gate (D18) formed on said second insulation film (D17) and serving as a word line (WL).
Claim 9
Dependent Claim
27 words
A semiconductor memory device according to claim 1, characterized in that said dummy capacitance cell (DC) is formed with the same structure as said memory cell (MC).
Claim 10
Dependent Claim
51 words
A semiconductor memory device according to claim 8, characterized in that each of said dummy capacitance cells (DC) includes a floating gate type MOS transistor which has a drain diffusion region (D11) connected to said dummy bit line (DBL) and a source diffusion region (D12) set in the electrically floating condition.
Claim 11
Dependent Claim
64 words
A semiconductor memory device according to claim 1, characterized by further comprising sense amplifier means (SA) for comparing a potential read out from a selected one of said data storing memory cells (MC) on to said bit line (BL) with a potential read out from said dummy cell (DMC) on to said dummy bit line (DBL) and amplifying the difference between the compared potentials.
Claim 12
Dependent Claim
56 words
A semiconductor memory device according to claim 10, characterized in that said sense amplifier means (SA) includes a differential amplifier (22); a first bias circuit/load circuit (21) connected to a first input terminal of said differential amplifier (22) and a second bias circuit/load circuit (23) connected to a second input terminal of said differential amplifier (22).
References Cited (Backward Citations)
No citation records indexed.
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