Multi-level state language controller for multi-threaded machine control

Claim 1

A multilevel state control system for an NC machine, comprising, in combination, a personal computer having an operating system for driving peripheral units of said personal computer, said peripheral units including at least a keyboard and monitor for input and output from said personal computer, an I/O unit adapted to receive data inputs and transmit data outputs over one or more data lines, said personal computer having memory means for storing a control program for controlling said peripheral units, at least one programmable personal automation control unit connected to the said I/O unit of said personal computer, and having a microprocessor unit and memory means for storing a program of operations for said microprossessor unit, and I/O means interconnecting said microprocessor unit with said one or more data lines, whereby the program of operations for said microprocessor is downloaded to said programmable personal automation control unit from said personal computer, a plurality of I/O modules connected to said personal automation control circuit and connected to said machine for supplying inputs to said machine and for deriving output signals from said machine, said control program of said personal computer being organized in a plurality of sequences, each said sequence having a plurality of successive states each described by a state descriptor, and said program of operations being made up of a plurality of state descriptors for each said sequence, each said state descriptor incorporating one or more instructions for said personal computer and an operation time, said personal computer having means for selecting each of said sequences in consecutive order and executing the instructions of one state of each sequence before selecting the next successive sequence, and means responsive to a priority instruction incorporated in one of said state descriptors for inhibiting the selection of the next successive sequence, and for executing the instructions incorporated in successive state descriptors of a single sequence.

Claim 3

A system for controlling a NC machine comprising, in combination, a personal computer having a microprocessor and a memory for storing a program of operations performed by said microprocessor, said program comprising a plurality of sequences, each having a plurality of successive state descriptors, with each of said state descriptors having at least one instruction to be performed by said microprocessor and an operational time, said personal computer having means for each said sequence to identify the location in memory of the current state of such sequence, means for designating one and only one state descriptor of each said sequence as the current state descriptor, means for executing the instructions in said current state descriptor of each sequence in turn, means responsive to the expiration of the said operational time of a state descriptor to designate the next successive state as the current state in that sequence, means responsive to a priority start instruction in a state descriptor for successively executing the instructions in successive state descriptors of the same sequence until a priority halt instruction is recognized, and thereafter resuming the execution of the instructions of one state from each successive sequence.

Claim 4

A system for controlling a NC machine comprising, in combination, a personal computer having a microprocessor and a memory for storing a program of operations performed by said microprocessor, said program comprising a plurality of sequences, each having a plurality of successive state descriptors, with each of said state descriptors having at least one instruction to be performed by said microprocessor and an operational time, said personal computer having means for each said sequence to identify the location in memory of the current state of such sequence, means for designating one and only one state descriptor of each said sequence as the current state descriptor, means for executing the instructions in said current state descriptor of each sequence in turn, means responsive to the expiration of the said operational time of a state descriptor to designate the next successive state as the current state in that sequence, means responsive to a priority start instruction in a state descriptor for successively executing the instructions in successive state descriptors of the same sequence until a priority halt instruction is recognized, and thereafter resuming the execution of the instructions of one state from each successive sequence.