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US5239262A
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Integrated circuit chip with built-in self-test for logic fault detection
Assignee: International Business Machines Corp
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Filing: 1992-02-21
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Granted: 1993-08-24
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Expires: 2012-02-21
Abstract
Abstract An integrated circuit chip with built-in self-test for logic fault detection is described which comprises a number of combinational logic circuits and a number of shift register latches. The combinational logic circuits are coupled via the shift register latches and the shift register latches are connected to form test scan paths. Test weights are created and combined with test patterns and are then applied to the test scan paths of the integrated circuit chip. In contrast to the prior art where the test weights are taken out of a weight storage table, the invention generates the test weights with the help of a so-called "finite state machine", i.e. with a circuit which creates a finite number of test weights without storing them. Therefore, no weight storage table or the like is necessary and the whole tester can be incorporated on the chip.
Inventors
- 👤 Matthias Grutzner
- 👤 Cordt W. Starke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
83 words
An integrated circuit chip with built-in self-test for logic fault detection comprising: at least one combinational logic circuit; a pattern generation circuit for generating test patterns; a weight generation circuit including a finite state machine for generating test weights; and a weighting circuit, said weighting circuit being coupled to said pattern generation circuit, said weight generation circuit and said combinational logic circuit for combining said test patterns and said test weights to create weighted test patterns for suppling to said combinational logic circuit.
Claim 2
Dependent Claim
83 words
An integrated circuit chip with built-in self-test for logic fault detection comprising: at least one combinational logic circuit; a pattern generation circuit for generating test patterns; a weight generation circuit including a finite state machine for generating test weights; and a weighting circuit, said weighting circuit being coupled to said pattern generation circuit, said weight generation circuit and said combinational logic circuit for combining said test patterns and said test weights to create weighted test patterns for suppling to said combinational logic circuit.
Claim 3
Dependent Claim
17 words
The integrated circuit chip according to claim 1 wherein said weight generation circuit comprises a shift register.
Claim 4
Dependent Claim
17 words
The integrated circuit chip according to claim 1 wherein said weight generation circuit comprises a counter register.
Claim 5
Dependent Claim
34 words
The integrated circuit chip according to claim 1 wherein said weight generation circuit comprises a number of bits which is about the same as the average width of all logic cones of the chip.
Claim 6
Dependent Claim
34 words
The integrated circuit chip according to claim 2 wherein said weight generation circuit comprises a number of bits which is about the same as the average width of all logic cones of the chip.
Claim 7
Dependent Claim
34 words
The integrated circuit chip according to claim 3 wherein said weight generation circuit comprises a number of bits which is about the same as the average width of all logic cones of the chip.
Claim 8
Dependent Claim
15 words
The integrated circuit chip according to claim 4, wherein said number of bits is 40.
Claim 9
Dependent Claim
44 words
The integrated circuit chip according to one of claim 1 wherein said weight generation circuit generates values of test weights which create weighted test patterns with an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent.
Claim 10
Dependent Claim
44 words
The integrated circuit chip according to one of claim 2 wherein said weight generation circuit generates values of test weights which create weighted test patterns with an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent.
Claim 11
Dependent Claim
44 words
The integrated circuit chip according to one of claim 3 wherein said weight generation circuit generates values of test weights which create weighted test patterns with an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent.
Claim 12
Dependent Claim
71 words
The-integrated circuit chip according to claim 1 wherein said weight generation circuit generates values of test weights which create weighted test patterns with a part of said weighted test patterns having an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent and with the rest of said weighted test patterns having an average percentage of binary "1" signals which is about 50 percent.
Claim 13
Dependent Claim
72 words
The integrated circuit chip according to claim 2 wherein said weight generation circuit generates values of test weights which create weighted test patterns with a part of said weighted test patterns having an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent and with the rest of said weighted test patterns having an average percentage of binary "1" signals which is about 50 percent.
Claim 14
Dependent Claim
72 words
The integrated circuit chip according to claim 3 wherein said weight generation circuit generates values of test weights which create weighted test patterns with a part of said weighted test patterns having an average percentage of binary "1" signals which is close to 0 percent or close to 100 percent and with the rest of said weighted test patterns having an average percentage of binary "1" signals which is about 50 percent.
Claim 15
Dependent Claim
19 words
The integrated circuit chip according to claim 8 wherein said average percentage of binary "1" signals is 12.5 percent.
Claim 16
Dependent Claim
19 words
The integrated circuit chip according to claim 11 wherein said average percentage of binary "1" signals is 12.5 percent.
Claim 17
Dependent Claim
19 words
The integrated circuit chip according to claim 8 wherein said average percentage of binary "1" signals is 87.5 percent.
Claim 18
Dependent Claim
19 words
The integrated circuit chip according to claim 11 wherein said average percentage of binary "1" signals is 87.5 percent.
Claim 19
Dependent Claim
36 words
The integrated circuit chip according to claim 1 wherein said weight generation circuit generates values of test weights which create weighted test patterns for adjacent signals with the same average number of binary "1's" or "0's".
Claim 20
Dependent Claim
25 words
The Integrated circuit chip according to claim 1 wherein said pattern generation circuit and said weight generation circuit are combined in one finite state machine.
Claim 21
Dependent Claim
89 words
An integrated circuit chip with built-in self-test for logic fault detection, for use in a computer system comprising: at least one combinational logic circuit; a pattern generation circuit for generating test patterns; a weight generation circuit including a finite state machine for generating test weights; and a weighting circuit, said weighting circuit being coupled to said pattern generation circuit, said weight generation circuit and said combinational logic circuit for combining said test patterns and said test weights to create weighted test patterns for suppling to said combinational logic circuit.
Claim 22
Dependent Claim
89 words
An integrated circuit chip with built-in self-test for logic fault detection, for use in a computer system comprising: at least one combinational logic circuit; a pattern generation circuit for generating test patterns; a weight generation circuit including a finite state machine for generating test weights; and a weighting circuit, said weighting circuit being coupled to said pattern generation circuit, said weight generation circuit and said combinational logic circuit for combining said test patterns and said test weights to create weighted test patterns for suppling to said combinational logic circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |