US5238869A
Expired / Lapsed
US
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Method of forming an epitaxial layer on a heterointerface
Assignee: Texas Instruments Inc
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Filing: 1992-07-27
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Granted: 1993-08-24
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Expires: 2012-07-27
Abstract
Abstract Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).
Inventors
- 👤 Hisashi Shichijo
- 👤 Richard J. Matyi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:24
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/3252; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; H10P14/36; Y; Y10; Y10S; Y10S438/00; Y10S438/933; Y10S438/938
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
112 words
A method of forming an epitaxial layer on a heterointerface having a minimum of dislocations propagating to or near the outer surface of said epitaxial layer in the region wherein devices will be fabricated, comprising the steps of: a) providing a substrate having a heterointerface thereon whereat most dislocations are generated and propagate up to about 20 μm and a grid at said heterointerface for absorbing said dislocations, said grid composed of intersecting lines forming quadrilaterals, the distance between opposing sides of each quadrilateral being about 10 μm; and b) growing a semiconductor layer on said grid and said heterointerface, said growth characterized by single crystal regions on portions of said heterointerface.
Claim 2
Independent Claim
112 words
A method of forming an epitaxial layer on a heterointerface having a minimum of dislocations propagating to or near the outer surface of said epitaxial layer in the region wherein devices will be fabricated, comprising the steps of: a) providing a substrate having a heterointerface thereon whereat most dislocations are generated and propagate up to about 20 μm and a grid at said heterointerface for absorbing said dislocations, said grid composed of intersecting lines forming quadrilaterals, the distance between opposing sides of each quadrilateral being about 10 μm; and b) growing a semiconductor layer on said grid and said heterointerface, said growth characterized by single crystal regions on portions of said heterointerface.
Claim 3
Dependent Claim
15 words
The method of claim 1, comprising the further step of: a) annealing said semiconductor layer.
Claim 4
Dependent Claim
44 words
The method of claim 2, wherein: a) said substrate is silicon; b) said grid is made of material from the group consisting of silicon dioxide, silicon nitride, and combinations thereof; and c) said semiconductor layer is Al x Ga 1-x As wherein 0≦x ≦1.0.
Claim 5
Dependent Claim
24 words
The method of claim 3 wherein said anneal is at a temperature of about 850° C. for about 15 minutes under an arsenic overpressure.
Claim 6
Dependent Claim
20 words
The method of claim 3, wherein said anneal is at a temperature of about 950° C. for about 10 seconds.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said guadrilateral is substantially a rectangle.
Claim 8
Independent Claim
102 words
A method of forming an epitaxial layer on a heterointerface having a minimum of dislocations propagating to or near the outer surface of said epitaxial layer in the region wherein devices will be fabricated, comprising the steps of: a) providing a semiconductor substrate having a heterointerface thereon whereat most dislocations are generated and propagate up to about 20 μm including a dislocation absorbing grid composed of intersecting and non-intersecting lines forming plural quadrilaterals at said heterointerface for absorbing said dislocations; and b) growing a continuous monocrystalline semiconductor layer extending over at least three adjacent non-intersecting lines of said grid and said surface.
Claim 9
Independent Claim
102 words
A method of forming an epitaxial layer on a heterointerface having a minimum of dislocations propagating to or near the outer surface of said epitaxial layer in the region wherein devices will be fabricated, comprising the steps of: a) providing a semiconductor substrate having a heterointerface thereon whereat most dislocations are generated and propagate up to about 20 μm including a dislocation absorbing grid composed of intersecting and non-intersecting lines forming plural quadrilaterals at said heterointerface for absorbing said dislocations; and b) growing a continuous monocrystalline semiconductor layer extending over at least three adjacent non-intersecting lines of said grid and said surface.
Claim 10
Dependent Claim
12 words
The method of claim 7 wherein said quadrilateral is substantially a rectangle.
Claim 11
Dependent Claim
20 words
The method of claim 7 wherein the distance between opposing sides of each of said quadrilaterals is about 10 μm.
Claim 12
Dependent Claim
20 words
The method of claim 8 wherein the distance between opposing sides of each of said quadrilaterals is about 10 μm.
Claim 13
Dependent Claim
23 words
The method of claim 1 further including forming an active semiconductor device in said semiconductor layer which extends over said dislocation absorbing grid.
Claim 14
Dependent Claim
24 words
The method of claim 7 further including forming an active semiconductor device in said monocrystalline semiconductor layer which extends over said dislocation absorbing grid.
References Cited (Backward Citations)
US4561916A
Cited
US4707216A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |