Microprogram load unit having alternative backup memory sources

Claim 1

An information processing system, comprising: a processing unit to which power is supplied for operation thereof and including a volatile first readable and writable memory unit for storing a microprogram, an arithmetic section for processing information under control of the microprogram stored in said first memory unit, and a power restoration detector for detecting when power is restored to the processing unit after power interruption; an external memory unit in the form of a second, relatively low speed, readable and writable, nonvolatile, memory unit for storing the microprogram which is stored in said first memory unit; a main memory unit including a volatile third readable and writable memory unit for storing the microprogram stored in said first memory unit and being connected to a backup battery, and detecting means for detecting loss of at least part of the microprogram stored in said third memory unit; a program transfer unit responsive to said power restoration detector for transferring said microprogram from said main memory unit or said external memory unit to said processing unit for storage in said first memory unit when power is restored to said processing unit, including transfer control means responsive to said detecting means detecting a loss of at least part of the microprogram stored in said third memory unit for transferring said microprogram from said second memory unit to said first memory unit and for otherwise transferring said microprogram from said third memory unit to said first memory unit when said detecting means indicates that the microprogram stored in said third memory means is valid; and a bus having address lines and data lines interconnecting said processing unit, said main memory and said program transfer unit; wherein said processing unit further includes a microprogram counter for generating access signals for accessing storage locations in said first memory unit to read out the microprogram in said first memory unit to said arithmetic section, a selector for connecting either said microprogram counter or the address lines of said bus to said first memory unit, and a loading admission flag unit responsive to said power restoration detector for controlling said selector to connect said address lines of said bus to said first memory unit when power to the processing unit is restored.