Formation of titanium nitride on semiconductor wafer by reaction of titanium with nitrogen-bearing gas in an integrated processing system

Claim 2

A process for forming a layer of substantially all titanium nitride on a semiconductor wafer which comprises: a) forming a titanium layer on said wafer in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; b) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; c) annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an initial annealing temperature of from 400° C. up to below about 600° C. for a period of from about 20 to about 60 seconds whereby substantially all of said titanium will react with said nitrogen to form said layer of substantially all titanium nitride on said wafer; and d) further annealing said wafer at a temperature of from about 800° C. to about 900° C. to form a stable phase of stoichiometric titanium nitride (TiN) on said wafer.

Claim 3

The process of claim 1 including the further steps of masking said titanium nitride layer after said annealing steps, and then selectively removing unmasked portions of said titanium nitride layer to thereby from a conductive titanium nitride pattern on said wafer.

Claim 4

The process of claim 1 wherein said nitrogen-bearing atmosphere in said annealing chamber is maintained, during said first annealing step, at a pressure ranging from about 100 milliTorr to about 800 Torr while flowing one or more nitrogen-bearing gases into said chamber at a rate ranging from about 500 to about 10,000 sccm.

Claim 5

The process of claim 1 wherein said nitrogen-bearing atmosphere in said annealing chamber is maintained, during said first annealing step, at a pressure ranging from about 500 milliTorr to about 10 Torr.

Claim 6

The process of claim 1 which further includes transferring said wafer from said vacuum deposition chamber to said sealed annealing chamber through a sealed central chamber maintained at a pressure ranging from about 10 -9 to about 10 -5 Torr which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber to avoid substantially exposing the newly formed titanium layer to oxygen and/or oxygen-bearing gases, whereby said titanium and said nitrogen will react to form said layer of substantially all titanium nitride within said initial annealing temperature range.

Claim 7

The process of claim 5 which comprises the further steps of: a) cleaning said wafer in a cleaning chamber using a gaseous mixture which includes at least one reactive gas while maintaining an rf plasma in said cleaning chamber to remove oxides and other materials from the silicon surfaces thereon prior to said titanium deposition step; and b) transferring said cleaned wafer from said cleaning chamber to said vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases using a sealed central chamber maintained at a pressure which ranges from about 10 -9 to about 10 -5 Torr which is interconnected to both said cleaning chamber and said vacuum deposition chamber.

Claim 8

The process of claim 6 wherein said cleaning step further comprises flowing into said cleaning chamber a gaseous mixture containing at least one reactive gas at a rate of from about 2 to about 500 sccm reactive gas and from about 10 to about 1000 sccm carrier gas while maintaining said plasma at a power ranging from about 20 to about 500 watts for a period of time ranging from about 1 to about 500 seconds.

Claim 9

The process of claim 7 including the further step of degassing said wafer, prior to said cleaning step, in a degassing chamber for from about 10 to about 180 seconds at a temperature of from about 50° C. to about 300° C. while maintaining a vacuum of from about 10 -5 to about 10 -9 Torr, and then transferring the degassed wafer to the cleaning chamber without exposing the wafer to oxygen-bearing gases.

Claim 10

The process of claim 1 wherein said titanium deposition step further comprises depositing a titanium layer ranging in thickness from about 100 to about 5000 Angstroms.

Claim 11

The process of claim 1 including the further step of forming titanium silicide portions over exposed silicon portions of said wafer prior to said step of depositing said titanium layer, whereby initially annealing of said titanium layer within said temperature range of from about 400° C. to below about 600° C. will result in the formation of titanium nitride over said titanium silicide portions, and subsequent patterning of said titanium nitride will form local interconnects between said titanium silicide portions and other parts of an integrated circuit structure formed on said wafer.

Claim 12

A process for forming a layer of substantially all titanium nitride on a semiconductor wafer having titanium silicide portions previously formed thereon which comprises: a) forming a titanium layer on said wafer and over said previously formed titanium silicide portions thereon in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; b) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; c) annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400° C. up to below about 600° C. for a period of from about 20 to about 60 seconds whereby substantially all of said titanium will react with said nitrogen to form said layer of substantially all titanium nitride on said wafer; d) further annealing said wafer at a temperature of from about 800° C. to about 900° C. for a period of from about 20 to about 60 seconds to form a stable phase of stoichiometric titanium nitride (TiN) on said wafer; e) masking said titanium nitride layer after said annealing steps; and f) then selectively removing unmasked portions of said titanium nitride layer to thereby form a conductive titanium nitride pattern on said wafer.

Claim 13

A process for forming a layer of substantially all titanium nitride on a semiconductor wafer having titanium silicide portions previously formed thereon which comprises: a) forming a titanium layer on said wafer and over said previously formed titanium silicide portions thereon in a vacuum deposition chamber in the substantial absence of oxygen-bearing gases; b) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; c) annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400° C. up to below about 600° C. for a period of from about 20 to about 60 seconds whereby substantially all of said titanium will react with said nitrogen to form said layer of substantially all titanium nitride on said wafer; d) further annealing said wafer at a temperature of from about 800° C. to about 900° C. for a period of from about 20 to about 60 seconds to form a stable phase of stoichiometric titanium nitride (TiN) on said wafer; e) masking said titanium nitride layer after said annealing steps; and f) then selectively removing unmasked portions of said titanium nitride layer to thereby form a conductive titanium nitride pattern on said wafer.

Claim 14

The process of claim 11 wherein said nitrogen-bearing atmosphere in said annealing chamber is maintained, during said first annealing step, at a pressure ranging from about from about 1 Torr to about 10 Torr.

Claim 15

The process of claim 11 wherein said step of transferring the titanium coated wafer to an annealing station without substantially exposing the newly formed titanium layer to oxygen-bearing gases further comprises transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber.

Claim 16

A process for forming a layer of substantially all titanium nitride on a semiconductor wafer which comprises: a) cleaning said wafer in a cleaning chamber for a period of time ranging from about 1 to about 500 seconds by flowing into the chamber a gaseous mixture containing at least one reactive gas at a rate of from about 2 to about 500 sccm reactive gas and from about 10 to about 1000 sccm carrier gas while maintaining a plasma at a power ranging from about 20 to about 500 watts; b) transferring said cleaned wafer from said cleaning chamber to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases using a sealed central chamber maintained at a pressure which ranges from about 10 -9 to about 10 -5 Torr which is interconnected to both said cleaning chamber and said vacuum deposition chamber; c) forming a titanium layer on said wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; d) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; e) annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400° C. up to below about 600° C. for a period of from about 20 to about 60 seconds whereby substantially all of said titanium will react with said nitrogen to form said layer of substantially all titanium nitride on said wafer; f) further annealing said wafer at a temperature of from about 800° C. to about 900° C. for a period of from about 20 to about 60 seconds to form a stable phase of stoichiometric titanium nitride (TiN) on said wafer; g) masking said titanium nitride layer after said annealing steps; and h) then selectively removing unmasked portions of said titanium nitride layer to thereby form a conductive titanium nitride pattern on said wafer.

Claim 17

A process for forming a layer of substantially all titanium nitride on a semiconductor wafer which comprises: a) cleaning said wafer in a cleaning chamber for a period of time ranging from about 1 to about 500 seconds by flowing into the chamber a gaseous mixture containing at least one reactive gas at a rate of from about 2 to about 500 sccm reactive gas and from about 10 to about 1000 sccm carrier gas while maintaining a plasma at a power ranging from about 20 to about 500 watts; b) transferring said cleaned wafer from said cleaning chamber to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases using a sealed central chamber maintained at a pressure which ranges from about 10 -9 to about 10 -5 Torr which is interconnected to both said cleaning chamber and said vacuum deposition chamber; c) forming a titanium layer on said wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases; d) transferring the titanium coated wafer to a sealed annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases; e) annealing the titanium-coated semiconductor wafer in a nitrogen-bearing atmosphere in said sealed annealing chamber, and in the substantial absence of oxygen-bearing gases, at an annealing temperature of from 400° C. up to below about 600° C. for a period of from about 20 to about 60 seconds whereby substantially all of said titanium will react with said nitrogen to form said layer of substantially all titanium nitride on said wafer; f) further annealing said wafer at a temperature of from about 800° C. to about 900° C. for a period of from about 20 to about 60 seconds to form a stable phase of stoichiometric titanium nitride (TiN) on said wafer; g) masking said titanium nitride layer after said annealing steps; and h) then selectively removing unmasked portions of said titanium nitride layer to thereby form a conductive titanium nitride pattern on said wafer.