US5233690A — Video graphics display memory swizzle logic and e…

Claim 1

Independent Claim 226 words

A system for adjusting bit positions of control data before presenting said control data to a memory bank including a plurality of planes of memory for storing fields of data, wherein each said field of data is associated with N inputs to said memory bank, said control data arriving on an input bus in ordinate positions that correspond on a one for one basis with said planes of memory, said planes of memory each being connected to a data bus in numerical order, said system comprising: reordering circuitry for reordering said bits of control data from said ordinate positions on said input bus to different ordinate positions on said data bus for application to said planes of memory, said reordering circuitry being a swizzle circuit having a plurality of inputs connected to said input bus and a like plurality of outputs connected to said planes of memory, said swizzle circuit comprising: a like plurality of latches, each latch controlling one input and one or more outputs; and circuitry for controlling which output any input is connected with at any instant of time; and expansion circuitry, operative prior to presentation of said control data to said reordering circuitry, for duplicating said control data from ordinate positions of said input bus N times and applying the duplicated control data through said reordering circuitry to said planes of memory.

Claim 2

Independent Claim 226 words

A system for adjusting bit positions of control data before presenting said control data to a memory bank including a plurality of planes of memory for storing fields of data, wherein each said field of data is associated with N inputs to said memory bank, said control data arriving on an input bus in ordinate positions that correspond on a one for one basis with said planes of memory, said planes of memory each being connected to a data bus in numerical order, said system comprising: reordering circuitry for reordering said bits of control data from said ordinate positions on said input bus to different ordinate positions on said data bus for application to said planes of memory, said reordering circuitry being a swizzle circuit having a plurality of inputs connected to said input bus and a like plurality of outputs connected to said planes of memory, said swizzle circuit comprising: a like plurality of latches, each latch controlling one input and one or more outputs; and circuitry for controlling which output any input is connected with at any instant of time; and expansion circuitry, operative prior to presentation of said control data to said reordering circuitry, for duplicating said control data from ordinate positions of said input bus N times and applying the duplicated control data through said reordering circuitry to said planes of memory.

Claim 3

Independent Claim 255 words

A system for adjusting the bit position of certain data input bits onto a data bus connected to a graphics memory comprising a number of VRAMs during a block-write operation of said graphics memory system, said block-write operation characterized by establishing with respect to each VRAM a color register having color bits representative of a color to be written to selective pixel locations represented at address locations within said VRAM, said VRAM having a number of planes, each plane having one data input lead and where a number of said planes operate together to control one pixel, said address selection occurring as a joint selection via the normal address leads of said VRAM and a 1 or 0 data bit on said data input leads of each plane of said VRAM such that each data input lead controls a different pixel, said data input leads connected to said data bus sequentially pixel by pixel. said data input bits arriving such that the ordinate position of each said bit is operable for presentation of a 1 or 0 to said pixels in like ordinate order, said system comprising; expansion circuitry for duplicating all said data input bits a number of times dependent upon the number of said VRAMs used for the control of said pixels, said expansion circuitry operating to expand said data input bits by adding said duplicated data bits in higher ordinate positions from the original data bits; and logic circuitry for reordering said bits after expansion for presentation to control said block-write operation.

Claim 4

Independent Claim 255 words

A system for adjusting the bit position of certain data input bits onto a data bus connected to a graphics memory comprising a number of VRAMs during a block-write operation of said graphics memory system, said block-write operation characterized by establishing with respect to each VRAM a color register having color bits representative of a color to be written to selective pixel locations represented at address locations within said VRAM, said VRAM having a number of planes, each plane having one data input lead and where a number of said planes operate together to control one pixel, said address selection occurring as a joint selection via the normal address leads of said VRAM and a 1 or 0 data bit on said data input leads of each plane of said VRAM such that each data input lead controls a different pixel, said data input leads connected to said data bus sequentially pixel by pixel. said data input bits arriving such that the ordinate position of each said bit is operable for presentation of a 1 or 0 to said pixels in like ordinate order, said system comprising; expansion circuitry for duplicating all said data input bits a number of times dependent upon the number of said VRAMs used for the control of said pixels, said expansion circuitry operating to expand said data input bits by adding said duplicated data bits in higher ordinate positions from the original data bits; and logic circuitry for reordering said bits after expansion for presentation to control said block-write operation.

Claim 5

Dependent Claim 71 words

A system as set forth in claim 2, wherein said logic circuitry is a swizzle circuit having a plurality of inputs and a like plurality of outputs, said swizzle circuit comprising: a like plurality of latches, each latch controlling one input connected to said expansion circuitry and one or more outputs connected to said planes; and circuitry for controlling which output any input is connected with at any instant of time.

Claim 6

Dependent Claim 33 words

The system set forth in claim 2 further including circuitry for determining the number of said VRAMs containing the same pixel information and for controlling said expansion circuitry in accordance with said determination.

Claim 7

Dependent Claim 31 words

The system set forth in claim 2 wherein said expansion circuitry is arranged for controlling the expansion when said graphics memory is configured with any number of VRAMs controlling said pixels.

Claim 8

Dependent Claim 438 words

A circuit for reordering the bit positions of a compressed data word for presenting said bits of said compressed data word to individual data leads of a data bus having b data leads therein, said presentation being in a plurality of modes and said presentation including the presentation of b data bits to said data but during any one memory write cycle, the circuit comprising: presentation registers for holding in sequence said data bits of said compressed data word for presentation to finite inputs of a series of memories, each memory having individual memory units, each memory unit having n data inputs, each data input connected in sequence to said b data leads of said data bus; such that in a first mode presentation, the memory units function as distinct memories when the ordinate positions of the first b/n data bits in said presentation register are associated with a first data input of each of said memories, the ordinate positions of the second b/n data bits in said presentation register are associated with a second data input of each of said memories, the ordinate position of the third b/n data bits in said presentation register are associated with a third data input of each of said memories, and the ordinate positions of the fourth b/n data bits in said presentation register are associated with a fourth data input of each of said memories; such that in a second mode presentation, said memory units function as pairs wherein the ordinate positions of the first (b/n)2 data bits in said presentation register are associated with the first data input of each of said memory pairs, the ordinate positions of the second (b/n)2 data bits in said presentation register are associated with the second data input of each of said memory pairs, the ordinate positions of the third (b/n)2 data bits in said presentation register are associated with the third data input of each of said memory pairs, and the ordinate position of the fourth (b/n)2 data bits in said presentation register are associated with the fourth input of each of said memory pairs, and wherein said circuit further comprises: expansion circuitry for duplicating in said presentation register the data bit from any ordinate position of said b data bits compressed data word into the next ordinate position in said presentation register when said memories are in said second mode; and reordering circuitry common to both said first and second modes for rearranging said data bits of said word in said presentation register during presentation of said data bits to said b data bus connections so as to effectuate said associations.

Claim 9

Dependent Claim 438 words

A circuit for reordering the bit positions of a compressed data word for presenting said bits of said compressed data word to individual data leads of a data bus having b data leads therein, said presentation being in a plurality of modes and said presentation including the presentation of b data bits to said data but during any one memory write cycle, the circuit comprising: presentation registers for holding in sequence said data bits of said compressed data word for presentation to finite inputs of a series of memories, each memory having individual memory units, each memory unit having n data inputs, each data input connected in sequence to said b data leads of said data bus; such that in a first mode presentation, the memory units function as distinct memories when the ordinate positions of the first b/n data bits in said presentation register are associated with a first data input of each of said memories, the ordinate positions of the second b/n data bits in said presentation register are associated with a second data input of each of said memories, the ordinate position of the third b/n data bits in said presentation register are associated with a third data input of each of said memories, and the ordinate positions of the fourth b/n data bits in said presentation register are associated with a fourth data input of each of said memories; such that in a second mode presentation, said memory units function as pairs wherein the ordinate positions of the first (b/n)2 data bits in said presentation register are associated with the first data input of each of said memory pairs, the ordinate positions of the second (b/n)2 data bits in said presentation register are associated with the second data input of each of said memory pairs, the ordinate positions of the third (b/n)2 data bits in said presentation register are associated with the third data input of each of said memory pairs, and the ordinate position of the fourth (b/n)2 data bits in said presentation register are associated with the fourth input of each of said memory pairs, and wherein said circuit further comprises: expansion circuitry for duplicating in said presentation register the data bit from any ordinate position of said b data bits compressed data word into the next ordinate position in said presentation register when said memories are in said second mode; and reordering circuitry common to both said first and second modes for rearranging said data bits of said word in said presentation register during presentation of said data bits to said b data bus connections so as to effectuate said associations.

Claim 10

Dependent Claim 40 words

The circuit set forth in claim 6 wherein said circuit further includes circuitry for shifting said data bits of said compressed word when said memories are in said second mode so that b data bits cycle through said presentation registers.

Claim 11

Dependent Claim 28 words

The circuit set forth in claim 6 further including circuitry for determining the mode of said memories and for controlling said expansion circuitry in accordance with said determination.

Claim 12

Dependent Claim 26 words

The circuit set forth in claim 6 wherein said expansion circuitry is arranged for controlling the expansion when said memory units function together as multiple pairs.

Claim 13

Dependent Claim 71 words

The circuit set forth in claim 6 wherein said reordering circuitry is a swizzle circuit having a plurality of inputs and a like plurality of outputs, said swizzle circuit comprising: a like plurality of latches, each latch controlling one input connected to said expansion circuitry and one or more outputs connected to said memory units; and circuitry for controlling which output any input is connected with at any instant of time.

Claim 14

Independent Claim 444 words

A method of reordering the bit positions of a compressed data word for presenting said bits of said data word to individual data leads to a data bus having b data leads therein, said presentation being in one of a plurality of modes and said presentation including the presentation of b data bits to said data bus during any one memory write cycle, said method comprising the steps of: holding in sequence said data bits of said compressed data word for presentation to finite inputs of a series of memories, each memory having individual memory units, each memory unit having n data inputs, each data input connected in sequence to said b data leads of said data bus; such that in a first mode presentation, the memory units function as distinct memories wherein the ordinate positions of the first b/n data bits in said held sequence bits are associated with a first data input of each of said memories, the ordinate positions of the second b/n data bits in said held sequence bits are associated with a second data input of each of said memories, the ordinate positions of the third b/n data bits in said held sequence bits are associated with a third data input of each of said memories, and the ordinate positions of the fourth b/n data bits in said held sequence bits are associated with a fourth data input of each of said memories, such that in a second mode presentation, said memory units function as pairs of memories wherein the ordinate positions of the first (b/n)2 data bits in said held sequence bits are associated with the first data input of each of said memory pairs, the ordinate positions of the second (b/n)/2 data bits in said held sequence bits are associated with the second data input of each of said memory pairs, the ordinate positions of the third (b/n)2 data bits in said held sequence bits are associated with the third data input of each of said memory pairs, and the ordinate positions of the fourth (b/n)2 data bits in said held sequence bits are associated with the fourth data input of each of said memory pairs, and wherein said method further comprises the steps of: duplicating the data from any ordinate position of said b bit sequentially held data into the next ordinate position in said held sequential data when said memories are in said second mode; and reordering said bits of said sequentially held bits during presentation of said bits to said b data bus connections so as to effectuate said associations, said reordering being the same for said first mode and for said second mode.

Claim 15

Independent Claim 444 words

A method of reordering the bit positions of a compressed data word for presenting said bits of said data word to individual data leads to a data bus having b data leads therein, said presentation being in one of a plurality of modes and said presentation including the presentation of b data bits to said data bus during any one memory write cycle, said method comprising the steps of: holding in sequence said data bits of said compressed data word for presentation to finite inputs of a series of memories, each memory having individual memory units, each memory unit having n data inputs, each data input connected in sequence to said b data leads of said data bus; such that in a first mode presentation, the memory units function as distinct memories wherein the ordinate positions of the first b/n data bits in said held sequence bits are associated with a first data input of each of said memories, the ordinate positions of the second b/n data bits in said held sequence bits are associated with a second data input of each of said memories, the ordinate positions of the third b/n data bits in said held sequence bits are associated with a third data input of each of said memories, and the ordinate positions of the fourth b/n data bits in said held sequence bits are associated with a fourth data input of each of said memories, such that in a second mode presentation, said memory units function as pairs of memories wherein the ordinate positions of the first (b/n)2 data bits in said held sequence bits are associated with the first data input of each of said memory pairs, the ordinate positions of the second (b/n)/2 data bits in said held sequence bits are associated with the second data input of each of said memory pairs, the ordinate positions of the third (b/n)2 data bits in said held sequence bits are associated with the third data input of each of said memory pairs, and the ordinate positions of the fourth (b/n)2 data bits in said held sequence bits are associated with the fourth data input of each of said memory pairs, and wherein said method further comprises the steps of: duplicating the data from any ordinate position of said b bit sequentially held data into the next ordinate position in said held sequential data when said memories are in said second mode; and reordering said bits of said sequentially held bits during presentation of said bits to said b data bus connections so as to effectuate said associations, said reordering being the same for said first mode and for said second mode.

Claim 16

Dependent Claim 25 words

The method as set forth in claim 11 further comprising the step of dynamically determining which memory mode is being used for any memory cycle.

Claim 17

Dependent Claim 23 words

The method as set forth in claim 12 further comprising the step of adjusting said duplicating step in accordance with said dynamic determination.

Claim 18

Dependent Claim 67 words

The method as set forth in claim 11 wherein said duplicating step includes the steps of: duplicating each bit of said compressed word a number of times depending upon the number of memory units functioning together; and expanding said held sequential data bits by adding said each set of duplicated bits in the next ordinate positions to the original data bits of said sequentially held data bits.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-08-02	1997-02-01	1997-08-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-08-02	2001-02-01	2001-08-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-08-02	2005-02-01	2005-08-03	$7700.00	Window Closed / Lapsed

Video graphics display memory swizzle logic and expansion circuit and method

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