US5233616A
Expired / Lapsed
US
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Write-back cache with ECC protection
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-10-01
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Granted: 1993-08-03
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Expires: 2010-10-01
Abstract
Abstract This invention relates to a write-back cache which is protected with parity and error correction coding ("ECC"). The parity and ECC codes are generated by a memory interface when data is transferred by main memory to the central processing unit ("CPU") associated with the cache. Thus, all data originating in main memory will be parity and ECC encoded when it passes through the memory interface, and the data, and its related parity information and ECC codes will be stored in the cache. On the other hand, data which is taken from the cache and modified by the CPU during its processing operations is also transferred to the memory interface for ECC encoding. Thus, all data modified by the CPU is also protected, and the modified data, and its related parity information and ECC codes are also stored in the cache. The memory interface also contains ECC checking and correcting circuitry which can correct erroneous data, on the basis of its ECC code, if that data has been corrupted while stored in the cache, or during transmission on a bus. Therefore, if data in the cache is corrupted, it can be corrected when it is returned to main memory via the memory interface. Accordingly, the invention makes a write-back cache compatible with full ECC protection, even though, at times, the cache may contain the only correct, current copy of given data in the system.
Inventors
- 👤 Michael A. Callander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:00
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F11/1044
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
291 words
A device for interfacing a central processing unit ("CPU") and a cache to a system bus, the CPU having the ability to generate parity information which corresponds to data modified by the CPU, said device comprising: a first bus for transferring data and parity information corresponding to the data, said first bus being connectable to the cache and the CPU; a second bus for transferring Error Correction Codes ("ECC") corresponding to the data, said second bus being connectable to the cache; a third bus for transferring data, said third bus being connectable to the system bus; an ECC generator/checker/corrector means for generating and checking the ECC corresponding to the data, and for correcting corrupt data by reference to the data and its corresponding ECC; a parity generator, said parity generator being capable of generating a parity code corresponding to the data transferred to said device over the system bus for storage in the cache; a parity checker, said parity checker being capable of checking and detecting parity errors in the data transferred to the device from the CPU by reference to the data and its corresponding parity code when modified data is transferred to the device by the CPU for ECC encoding; first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said third bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bi-directional buffer; said second bi-directional buffer being coupled to said first and second buses; and said ECC checker/corrector means, said parity generator, and said parity checker being coupled between said first and second bi-directional buffers.
Claim 2
Independent Claim
291 words
A device for interfacing a central processing unit ("CPU") and a cache to a system bus, the CPU having the ability to generate parity information which corresponds to data modified by the CPU, said device comprising: a first bus for transferring data and parity information corresponding to the data, said first bus being connectable to the cache and the CPU; a second bus for transferring Error Correction Codes ("ECC") corresponding to the data, said second bus being connectable to the cache; a third bus for transferring data, said third bus being connectable to the system bus; an ECC generator/checker/corrector means for generating and checking the ECC corresponding to the data, and for correcting corrupt data by reference to the data and its corresponding ECC; a parity generator, said parity generator being capable of generating a parity code corresponding to the data transferred to said device over the system bus for storage in the cache; a parity checker, said parity checker being capable of checking and detecting parity errors in the data transferred to the device from the CPU by reference to the data and its corresponding parity code when modified data is transferred to the device by the CPU for ECC encoding; first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said third bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bi-directional buffer; said second bi-directional buffer being coupled to said first and second buses; and said ECC checker/corrector means, said parity generator, and said parity checker being coupled between said first and second bi-directional buffers.
Claim 3
Dependent Claim
57 words
A device as in claim 1 further comprising a write-back queue and an address/data multiplexor; said second bi-directional buffer being coupled to said ECC check/correct means; said ECC check/correct means being coupled to said write-back queue; said write-back queue being coupled to said address/data multiplexor; and said address data multiplexor being coupled to said first bi-directional buffer.
Claim 4
Independent Claim
303 words
An apparatus adapted for connection between a central processing unit ("CPU") and a system bus, the CPU having the ability to generate parity information which corresponds to data modified by the CPU, said apparatus comprising: a memory means for storing data and Error Correction Codes ("ECC") corresponding to the the data; a first bus for transferring data and parity information corresponding to the data, said first bus being coupled with said memory means and connectable with the CPU; a second bus for transferring the ECC corresponding to the data, said second bus being coupled to said memory means; a third bus for transferring data, said third bus being connectable to the system bus; a means for interfacing the CPU to the system bus comprising: an ECC generator/checker/corrector means for generating and checking the ECC corresponding to the data, and for correcting corrupt data by reference to the data and its corresponding ECC; a parity generator, said parity generator being capable of generating a parity code corresponding to the data transferred to said interfacing means over the system bus for storage in said memory means; a parity checker, said parity checker being capable of checking and detecting parity errors in the data transferred to said interfacing means from the CPU by reference to the data and its corresponding parity code when the data is transferred to said interfacing means by the CPU for ECC encoding; first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said third bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bidirectional buffer; and said second bi-directional buffer being coupled to said first and second buses.
Claim 5
Independent Claim
303 words
An apparatus adapted for connection between a central processing unit ("CPU") and a system bus, the CPU having the ability to generate parity information which corresponds to data modified by the CPU, said apparatus comprising: a memory means for storing data and Error Correction Codes ("ECC") corresponding to the the data; a first bus for transferring data and parity information corresponding to the data, said first bus being coupled with said memory means and connectable with the CPU; a second bus for transferring the ECC corresponding to the data, said second bus being coupled to said memory means; a third bus for transferring data, said third bus being connectable to the system bus; a means for interfacing the CPU to the system bus comprising: an ECC generator/checker/corrector means for generating and checking the ECC corresponding to the data, and for correcting corrupt data by reference to the data and its corresponding ECC; a parity generator, said parity generator being capable of generating a parity code corresponding to the data transferred to said interfacing means over the system bus for storage in said memory means; a parity checker, said parity checker being capable of checking and detecting parity errors in the data transferred to said interfacing means from the CPU by reference to the data and its corresponding parity code when the data is transferred to said interfacing means by the CPU for ECC encoding; first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said third bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bidirectional buffer; and said second bi-directional buffer being coupled to said first and second buses.
Claim 6
Dependent Claim
14 words
An apparatus as in claim 3, wherein said memory means comprises a write-back cache.
Claim 7
Dependent Claim
56 words
An apparatus as in claim 3 further comprising a write-back queue and an address/data multiplexor; said second bi-directional buffer being coupled to said ECC check/correct means; said ECC check/correct means being coupled to said write-back queue; said write-back queue being coupled to said address/data multiplexor; and said address/data multiplexor being coupled to said first bi-directional buffer.
Claim 8
Dependent Claim
420 words
A module which is connectable to a system bus, the system bus being coupled to a main memory and being capable of transferring addresses and data between said module and the main memory, said module comprising: an interface bus, connectable to the system bus; an address bus; a data/parity bus; an Error Correction Code ("ECC") bus; a central processing unit ("CPU"), having a means for checking parity errors in and generating parity information for data processed by said CPU, and said CPU being capable of invoking an error handling routine in response to detected parity errors; a write-back cache for storing information, said cache being coupled to said CPU through said address bus and said data/parity bus; and means for interfacing said CPU and said cache to the system bus, said interfacing means: being coupled to said CPU through said data/parity bus and said address bus; being coupled to said cache through said data/parity bus, said address bus, and said ECC bus; and being coupled to said interface bus; said interfacing means comprising: an ECC generator which is capable of generating an ECC for data transferred to the interfacing means by the CPU or over the system bus; an ECC checker which is capable of checking an ECC together with its corresponding data, and thereby detect corrupt data, when the data and its corresponding ECC are transferred to said interfacing means; an ECC corrector which is capable of correcting corrupt data by reference to the data and its corresponding ECC when the data and its corresponding ECC are transferred to said interfacing means; a parity generator which is capable of generating a parity code corresponding to the data such that when the data is transferred to said interfacing means the data is parity encoded and the data and its corresponding parity code are subsequently stored in said cache; a parity check which is capable of checking and detecting a parity error in the data by reference to the data and its corresponding parity code when the data is transferred to said interfacing means by the CPU for ECC encoding first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said interface bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bi-directional buffer; and said second bi-directional buffer being coupled to said data/parity bus and said ECC bus.
Claim 9
Dependent Claim
420 words
A module which is connectable to a system bus, the system bus being coupled to a main memory and being capable of transferring addresses and data between said module and the main memory, said module comprising: an interface bus, connectable to the system bus; an address bus; a data/parity bus; an Error Correction Code ("ECC") bus; a central processing unit ("CPU"), having a means for checking parity errors in and generating parity information for data processed by said CPU, and said CPU being capable of invoking an error handling routine in response to detected parity errors; a write-back cache for storing information, said cache being coupled to said CPU through said address bus and said data/parity bus; and means for interfacing said CPU and said cache to the system bus, said interfacing means: being coupled to said CPU through said data/parity bus and said address bus; being coupled to said cache through said data/parity bus, said address bus, and said ECC bus; and being coupled to said interface bus; said interfacing means comprising: an ECC generator which is capable of generating an ECC for data transferred to the interfacing means by the CPU or over the system bus; an ECC checker which is capable of checking an ECC together with its corresponding data, and thereby detect corrupt data, when the data and its corresponding ECC are transferred to said interfacing means; an ECC corrector which is capable of correcting corrupt data by reference to the data and its corresponding ECC when the data and its corresponding ECC are transferred to said interfacing means; a parity generator which is capable of generating a parity code corresponding to the data such that when the data is transferred to said interfacing means the data is parity encoded and the data and its corresponding parity code are subsequently stored in said cache; a parity check which is capable of checking and detecting a parity error in the data by reference to the data and its corresponding parity code when the data is transferred to said interfacing means by the CPU for ECC encoding first and second bi-directional buffers; a read queue; a read/write multiplexor; and said first bi-directional buffer being coupled to said interface bus and said read queue; said read queue being coupled to said read/write multiplexor; said read/write multiplexor being coupled to said ECC generator means; said ECC generator means being coupled to said second bi-directional buffer; and said second bi-directional buffer being coupled to said data/parity bus and said ECC bus.
Claim 10
Dependent Claim
56 words
A module as in claim 6 further comprising a write-back queue and an address/data multiplexor; said second bi-directional buffer being coupled to said ECC check/correct means; said ECC check/correct means being coupled to said write-back queue; said write-back queue being coupled to said address/data multiplexor; and said address/data multiplexor being coupled to said first bi-directional buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |