US5233603A
Expired / Lapsed
US
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Packet switch suitable for integrated circuit implementation
Assignee: NEC Corp
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Filing: 1991-10-08
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Granted: 1993-08-03
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Expires: 2011-10-08
Abstract
Abstract A packet switch for high-speed synchronous multiplexing of voice and picture communications collectively. The packet switch uses among other things an input multiplexer, and output demultiplexer, and a single buffer memory divided into memory areas connected to multiple input and output lines. The subdivided buffer is controlled by counters rather than a more complicated address exchanger. A second embodiment eliminates the need for an output demultiplexer because of individual read/write control of the buffer units. A third embodiment includes a bidirectional bus between an input buffer and an output buffer. A fourth embodiment uses a more economical unidirectional bus. The unidirectional bus can be limited to a part of an input packet to permit Large Scale Integration (LSI). In the LSI configuration, address filters may be replaced with a centralized address controller, and the buffer can consist of FiFo memory units or RAM units.
Inventors
- 👤 Takao Takeuchi
- 👤 Hiroshi Suzuki
- 👤 Susumu Iwasaki
- 👤 Hiroshi Nagano
- 👤 Toshio Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:20
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/10; H04L49/103; H04L49/30; H04L49/3018; H04L49/3027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
415 words
A packet switch, having a plurality of input lines and a plurality of output lines for exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: (a) a plurality of first serial-to-parallel converting means each being associated with a respective one of said input lines for converting a packet coming in over an associated one of said input lines to first parallel data having a first predetermined number of bits, while latching address information contained in said packet; (b) a plurality of unit packet exchanging means equal in number to said first predetermined number, each comprising (i) a plurality of second serial-to-parallel converting means each being associated with one of said plurality of first serial-to-parallel converting means for receiving an associated bit of said first parallel data as input serial data, for converting said input serial data into second parallel data having a second predetermined number of bits, (ii) a plurality of memory means each being associated with one of said output lines for storing said second parallel data, in response to a write signal, as stored data and for outputting said stored data at a predetermined period, (iii) first bus means for distributing said second parallel data to said plurality of memory means, and (iv) a plurality of first parallel-to-serial converting means each being associated with one of said plurality of memory means for converting said second parallel data to first serial data and outputting said first serial data as an associated bit of said first parallel data; and (c) address controller means comprising (i) a plurality of third serial-to-parallel converting means each being associated with one of said first serial-to-parallel converting means for converting said address information to parallel address data, (ii) a plurality of address filter means each being associated with one of said plurality of output lines for making a determination whether or not said parallel address data indicates said one of said output lines and, if the result of said determination is positive, outputting said write signals, and (iii) second bus means for distributing said parallel address data to said plurality address filter means; and (d) a plurality of second parallel-to-serial converting means being associated with respective ones of said plurality of output lines for reading said first serial data from said first parallel-to-serial converting means of said plurality of unit packet exchanging means for converting said first serial data to second serial data and delivering said second serial data as said exchanged packet.
Claim 2
Dependent Claim
415 words
A packet switch, having a plurality of input lines and a plurality of output lines for exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: (a) a plurality of first serial-to-parallel converting means each being associated with a respective one of said input lines for converting a packet coming in over an associated one of said input lines to first parallel data having a first predetermined number of bits, while latching address information contained in said packet; (b) a plurality of unit packet exchanging means equal in number to said first predetermined number, each comprising (i) a plurality of second serial-to-parallel converting means each being associated with one of said plurality of first serial-to-parallel converting means for receiving an associated bit of said first parallel data as input serial data, for converting said input serial data into second parallel data having a second predetermined number of bits, (ii) a plurality of memory means each being associated with one of said output lines for storing said second parallel data, in response to a write signal, as stored data and for outputting said stored data at a predetermined period, (iii) first bus means for distributing said second parallel data to said plurality of memory means, and (iv) a plurality of first parallel-to-serial converting means each being associated with one of said plurality of memory means for converting said second parallel data to first serial data and outputting said first serial data as an associated bit of said first parallel data; and (c) address controller means comprising (i) a plurality of third serial-to-parallel converting means each being associated with one of said first serial-to-parallel converting means for converting said address information to parallel address data, (ii) a plurality of address filter means each being associated with one of said plurality of output lines for making a determination whether or not said parallel address data indicates said one of said output lines and, if the result of said determination is positive, outputting said write signals, and (iii) second bus means for distributing said parallel address data to said plurality address filter means; and (d) a plurality of second parallel-to-serial converting means being associated with respective ones of said plurality of output lines for reading said first serial data from said first parallel-to-serial converting means of said plurality of unit packet exchanging means for converting said first serial data to second serial data and delivering said second serial data as said exchanged packet.
Claim 3
Dependent Claim
410 words
A packet switch having a plurality of input lines and a plurality of output lines, for exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: a plurality of first serial-to-parallel converting means each being associated with a respective one of said input lines for converting a packet coming in over an associated one of said input lines to first parallel data having a predetermined number of bits, while latching address information contained in said packet; a plurality of unit packet exchange means each being associated with a respective one of said bits of said first parallel data; and a plurality of first parallel-to-serial converting means being associated with a respective one of said plurality of output lines for reading said first parallel data out of an associated one of said memory means, converting said first parallel data to first serial data as an exchanged packet to an associated one of said output lines; each of said plurality of unit packet exchange means comprising, a plurality of second serial-to-parallel converting means each being associated with said plurality of first serial-to-parallel converting means for receiving associated bits of said first parallel data as input serial data, converting said input serial data into second parallel data having a second predetermined number of bits, combining said address information being latched by an associated one of said first serial-to-parallel converting means with said second parallel data to produce third parallel data; a plurality of address filter means each being associated with said plurality of output lines for determining whether or not said third parallel data is meant for said associated output line by referencing address information of said third parallel data and, if a result of a decision is positive, outputting said second parallel data by removing said address information from said third parallel data; bus means for distributing said third parallel data from one of said second serial-to-parallel converting means to all of said address filter means; memory means each being associated with said address filter means for holding as write data said second parallel data which is outputted by an associated one of said address filter means and outputting said write data at a predetermined period; and a plurality of second parallel-to-serial converting means each being associated with said memory means for converting said second parallel data outputted by an associated one of said memory means to second serial data and outputting said second serial data.
Claim 4
Dependent Claim
410 words
A packet switch having a plurality of input lines and a plurality of output lines, for exchanging packets received over said input lines and delivering exchanged packets to said output lines, comprising: a plurality of first serial-to-parallel converting means each being associated with a respective one of said input lines for converting a packet coming in over an associated one of said input lines to first parallel data having a predetermined number of bits, while latching address information contained in said packet; a plurality of unit packet exchange means each being associated with a respective one of said bits of said first parallel data; and a plurality of first parallel-to-serial converting means being associated with a respective one of said plurality of output lines for reading said first parallel data out of an associated one of said memory means, converting said first parallel data to first serial data as an exchanged packet to an associated one of said output lines; each of said plurality of unit packet exchange means comprising, a plurality of second serial-to-parallel converting means each being associated with said plurality of first serial-to-parallel converting means for receiving associated bits of said first parallel data as input serial data, converting said input serial data into second parallel data having a second predetermined number of bits, combining said address information being latched by an associated one of said first serial-to-parallel converting means with said second parallel data to produce third parallel data; a plurality of address filter means each being associated with said plurality of output lines for determining whether or not said third parallel data is meant for said associated output line by referencing address information of said third parallel data and, if a result of a decision is positive, outputting said second parallel data by removing said address information from said third parallel data; bus means for distributing said third parallel data from one of said second serial-to-parallel converting means to all of said address filter means; memory means each being associated with said address filter means for holding as write data said second parallel data which is outputted by an associated one of said address filter means and outputting said write data at a predetermined period; and a plurality of second parallel-to-serial converting means each being associated with said memory means for converting said second parallel data outputted by an associated one of said memory means to second serial data and outputting said second serial data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |