US5233241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semicustom made integrated circuit equipped with controller for input/output buffers
Assignee: NEC Corp
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Filing: 1991-11-25
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Granted: 1993-08-03
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Expires: 2011-11-25
Abstract
Abstract A semicustom made integrated circuit is fabricated from first function blocks completed before acceptance of an order from a customer, second function blocks completed after the acceptance of order, input/output buffer circuits coupled with the first function blocks, buffer circuits respectively associated with the second function blocks, and controlling circuits provided in association with the buffer circuits for shifting the associated buffer circuits between input buffer circuits, output buffer circuits, bidirectional buffer circuits and three-state buffer circuits, and the controlling circuits are instructed by the second function blocks while the manufacturer is designing the wiring arrangement of the second function blocks so that the manufacturer does not need to individually tailor the wiring arrangement between the second function blocks and the associated buffer circuits.
Inventors
- 👤 Hiroaki Nishimori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:38
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17764; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/17704; H03K19/17736; H03K19/17744; H03K19/1778
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
141 words
A semicustom made integrated circuit fabricated on a single semiconductor chip from logic gates and conductive wirings, comprising: a) at least one first function block a wiring arrangement of which has been completed so as to fix the function thereof before accepting an order of a customer; b) at least one second function block a wiring arrangement of which is completed so as to fix the function thereof after said acceptance of said order of said customer, said at least one second function block producing instruction signals indicative of what kind of buffer circuit is necessary for said function thereof; and c) at least one buffer circuit means associated with said at least one second function block, and selectively serving as one of an input buffer, an output buffer, a bidirectional buffer and a three-state buffer depending upon said instruction signals.
Claim 2
Dependent Claim
141 words
A semicustom made integrated circuit fabricated on a single semiconductor chip from logic gates and conductive wirings, comprising: a) at least one first function block a wiring arrangement of which has been completed so as to fix the function thereof before accepting an order of a customer; b) at least one second function block a wiring arrangement of which is completed so as to fix the function thereof after said acceptance of said order of said customer, said at least one second function block producing instruction signals indicative of what kind of buffer circuit is necessary for said function thereof; and c) at least one buffer circuit means associated with said at least one second function block, and selectively serving as one of an input buffer, an output buffer, a bidirectional buffer and a three-state buffer depending upon said instruction signals.
Claim 3
Dependent Claim
76 words
A semicustom made integrated circuit as set forth in claim 1, in which said buffer circuit means comprises a combination block of a three state buffer circuit and an input buffer circuit, and a controlling circuit block coupled between said combination block and said at least one second function block and responsive to said instruction signals for controlling said three-state buffer circuit and for transferring or blocking an input signal supplied from said input buffer circuit.
Claim 4
Dependent Claim
275 words
A semicustom made integrated circuit fabricated on a single semiconductor chip, comprising: a) at least one first function block a wiring arrangement of which has been completed so as to fix the function thereof before accepting an order of a customer; b) at least one second function block a wiring arrangement of which is completed so as to fix the function thereof after said acceptance of said order of said customer, said at least one second function block producing instruction signals indicative of what kind of buffer circuit is necessary for said function thereof; and c) at least one buffer circuit means associated with said at least one second function block, and selectively serving as one of an input buffer, an output buffer, a bidirectional buffer and a three-state buffer depending upon said instruction signals, said buffer circuit means comprising a combination block of a three-state buffer circuit and an input buffer circuit, and a controlling circuit block coupled between said combination block and said at least one second function block and responsive to said instruction signals for controlling said three-state buffer circuit and for transferring or blocking an input signal supplied from said input buffer circuit, said controlling circuit block comprising a first section responsive to said instruction signals for shifting said three-state buffer circuit between a high-impedance state and an active state, and causing said three-state buffer circuit to transfer an output signal from said at least one second function block to an associated pad in said active state, and a second section responsive to said instruction signals for transferring or blocking said input signal to said at least one second function block.
Claim 5
Dependent Claim
275 words
A semicustom made integrated circuit fabricated on a single semiconductor chip, comprising: a) at least one first function block a wiring arrangement of which has been completed so as to fix the function thereof before accepting an order of a customer; b) at least one second function block a wiring arrangement of which is completed so as to fix the function thereof after said acceptance of said order of said customer, said at least one second function block producing instruction signals indicative of what kind of buffer circuit is necessary for said function thereof; and c) at least one buffer circuit means associated with said at least one second function block, and selectively serving as one of an input buffer, an output buffer, a bidirectional buffer and a three-state buffer depending upon said instruction signals, said buffer circuit means comprising a combination block of a three-state buffer circuit and an input buffer circuit, and a controlling circuit block coupled between said combination block and said at least one second function block and responsive to said instruction signals for controlling said three-state buffer circuit and for transferring or blocking an input signal supplied from said input buffer circuit, said controlling circuit block comprising a first section responsive to said instruction signals for shifting said three-state buffer circuit between a high-impedance state and an active state, and causing said three-state buffer circuit to transfer an output signal from said at least one second function block to an associated pad in said active state, and a second section responsive to said instruction signals for transferring or blocking said input signal to said at least one second function block.
Claim 6
Dependent Claim
78 words
A semicustom made integrated circuit as set forth in claim 3, in which said first section comprises a first OR gate responsive to said instruction signals for producing a controlling signal supplied to a first inverting circuit coupled with a control node of said three-state buffer circuit, and a conductive path coupled with an output node of said at least one second function block for propagating said output signal to an input node of said three-state buffer circuit.
Claim 7
Dependent Claim
101 words
A semicustom made integrated circuit as set forth in claim 3, in which said second section comprises a second inverting circuit supplied with one of said instruction signals, a first AND gate supplied with an output signal of said second inverting circuit and the other of said instruction signals, a second AND gate supplied with said one of said instruction signals and said input signal, a second OR gate supplied with output signals of said first and second AND gates, and an exclusive-OR gate supplied with an output signal of said second OR gate and the other of said instruction signals.
Claim 8
Dependent Claim
29 words
A semicustom made integrated circuit as set forth in claim 5, in which each of said instruction signals is fixed to either a first or a second logic level.
Claim 9
Dependent Claim
23 words
A semicustom made integrated circuit as set forth in claim 5, in which each of said instruction signals is variable in logic level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |