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US5233235A
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On-chip intermediate driver for discrete WSI systems
Assignee: Qimonda AG
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Filing: 1992-07-28
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Granted: 1993-08-03
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Expires: 2012-07-28
Abstract
Abstract In discrete wafer-scale integration abbreviated as WSI, pre-tested chips are mounted and bonded on a pre-wired wafer. Silicon usually serves as the wafer substrate because the wafer wiring can be cost-beneficially produced with a standard multi-layer process. The conducting properties of such a wafer micro-wiring forbid the use of long leads given high timing clocks, so that intermediate drivers must be utilized. Previous solutions make use of separate driver chips that must be placed, bonded and tested in addition to the actual function chips. In the disclosed WSI system, the intermediate drivers are not realized as separate chips but are implemented on the function chip itself.
Inventors
- 👤 Ulrich Ramacher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
109 words
An intermediate driver apparatus for discrete wafer-scale integration systems in which a plurality of chips are mounted on a pre-wired wafer, the plurality of chips at least partially connected to one another via bonded chip leads and at least partially connected to inputs and outputs of the pre-wired wafer via bonded chip leads, comprising: at least one chip of the plurality of chips having a monolithically integrated large scale integration circuit and a monolithically integrated intermediate driver; the intermediate driver connected to at least one predetermined chip lead for the at least one chip of the plurality of chips in order to amplify signals on the predetermined chip lead.
Claim 2
Dependent Claim
109 words
An intermediate driver apparatus for discrete wafer-scale integration systems in which a plurality of chips are mounted on a pre-wired wafer, the plurality of chips at least partially connected to one another via bonded chip leads and at least partially connected to inputs and outputs of the pre-wired wafer via bonded chip leads, comprising: at least one chip of the plurality of chips having a monolithically integrated large scale integration circuit and a monolithically integrated intermediate driver; the intermediate driver connected to at least one predetermined chip lead for the at least one chip of the plurality of chips in order to amplify signals on the predetermined chip lead.
Claim 3
Dependent Claim
84 words
The intermediate driver apparatus for discrete wafer-scale integration systems according to claim 1, wherein the predetermined chip lead is connected to a first on-chip pad on the at least one chip of the plurality of chips and wherein an input of the intermediate driver is connected to the first on-chip pad on the at lest one chip of the plurality of chips and an output thereof is connected to an additional on-chip pad on the at least one chip of the plurality of chips.
Claim 4
Dependent Claim
37 words
The intermediate driver apparatus for discrete wafer-scale integration systems according to claim 1, wherein inputs and outputs of the intermediate driver are connected to on-chip pads on the at least one chip of the plurality of chips.
Claim 5
Dependent Claim
40 words
The intermediate driver apparatus for discrete wafer-scale integration systems according to claim 1, wherein, the at least one chip of the plurality of chips is constructed in CMOS technology, and the intermediate driver is formed of two series-connected inverter stages.
Claim 6
Dependent Claim
170 words
The intermediate driver apparatus for discrete wafer-scale integration systems according to claim 4, wherein the two inverter stages each respectively contain a p-channel and an n-channel MOS field effect transistor; wherein first terminals of the n-channel MOS field effect transistors, of the first and second inverter stages are respectively connected to ground and first terminals of the p-channel MOS field effect transistors of the first and second inverter stages are respectively connected to a supply voltage; wherein gate terminals of the n-channel and p-channel MOS field effect transistors of the first inverter stage form an input of the intermediate driver; wherein second terminals of the n-channel and p-channel MOS field effect transistors of the first inverter stage are connected to one another and to gate terminals of the p-channel and n-channel MOS field effect transistors of the second inverter stage; wherein second terminals of the p-channel and n-channel MOS field effect transistors of the second inverter stage are connected to one another and form an output of the intermediate driver.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |