Semiconductor memory device

Claim 2

A semiconductor memory device, comprising: a semiconductor chip; a memory cell array region on said semiconductor chip including a memory cell array having memory cells; signal lines arranged on a surface of said semiconductor chip above said memory cell array; power conductor lines arranged on a surface of said semiconductor chip above said memory cell array, each of said power conductor lines having a first end, a second end, and a portion extending between adjacent ones of said signal lines, the first ends of said power conductors connected together and the second ends of said power conductors connected together.

Claim 3

A semiconductor memory device according to claim 1, wherein at least one of the first and second ends of each power conductor is connected to a power conductor pad.

Claim 4

A semiconductor memory device according to claim 1, wherein said signal lines are column-selecting lines.

Claim 5

A semiconductor memory device according to claim 1, wherein said signal lines are column signal reading/writing lines.

Claim 6

The semiconductor memory device according claim 1, wherein said power conductor lines include power-supply lines.

Claim 7

The semiconductor memory device according to claim 1, wherein said power conductor lines include ground lines.

Claim 8

The semiconductor memory device according to claim 1, wherein said signal lines are signal lines for supplying signals to memory cells of said array.

Claim 9

A semiconductor memory device, comprising: a semiconductor chip; two memory cell array regions on said semiconductor chip each including a memory cell array having memory cells; a peripheral circuit region between said two memory cell array regions; signal lines arranged on a surface of said semiconductor chip above said memory cell array regions; a first arrangement of power-supply lines, each of which has a first end, a second end, and a portion disposed between adjacent ones of said signal lines and each of which is connected to said peripheral circuit region; and a second arrangement of ground lines, each of which has a first end and a second end, and a portion disposed between adjacent ones of said signal lines and each of which is connected to said peripheral circuit region, wherein both the first and second ends of each line in at least one of said first and second arrangements are respectively connected together.

Claim 10

A semiconductor memory device, comprising: a semiconductor chip; two memory cell array regions on said semiconductor chip each including a memory cell array having memory cells; a peripheral circuit region between said two memory cell array regions; signal lines arranged on a surface of said semiconductor chip above said memory cell array regions; a first arrangement of power-supply lines, each of which has a first end, a second end, and a portion disposed between adjacent ones of said signal lines and each of which is connected to said peripheral circuit region; and a second arrangement of ground lines, each of which has a first end and a second end, and a portion disposed between adjacent ones of said signal lines and each of which is connected to said peripheral circuit region, wherein both the first and second ends of each line in at least one of said first and second arrangements are respectively connected together.

Claim 11

A semiconductor memory device according to claim 8, wherein at least one of the first and second ends of each power-supply line is connected to a power-supply pad.

Claim 12

A semiconductor memory device according to claim 8, wherein at least one of the first and second ends of each ground line is connected to a ground pad.

Claim 13

A semiconductor memory device according to claim 8, wherein said power-supply lines are connected to one another above the peripheral circuit region.

Claim 14

A semiconductor memory device according to claim 8, wherein said ground lines are connected to one another above the peripheral circuit region.

Claim 15

A semiconductor memory device according to claim 8, wherein said signal lines are column-selecting lines.

Claim 16

A semiconductor memory device according to claim 8, wherein said signal lines are column signal reading/writing lines.

Claim 17

The semiconductor memory device according to claim 10, wherein one of said power supply lines and one of said ground lines are arranged between adjacent ones of said signal lines.