Videographics display system

Claim 1

A videographics display system including: processing means adapted to control the operation of said display system; video random access memory means adapted to store video data and non-video data dispersed from the video data by non-contiguous storage areas to be displayed; monitor means adapted to provide a visual display of the stored data including memory control means coupled to said processing means and to said memory means and adapted to address said memory means in a first mode to access a first portion of said memory means which is adapted to store video data to be displayed on said monitor means and in a second mode to access a second portion of said memory means adapted to store non-video data, wherein said second portion includes storage locations dispersed in a plurality of dispersed storage locations in said memory means and wherein said memory control means is adapted to address said second portion of said memory means by means of contiguous addresses, said memory control means including means for generating first and second mode control signals for use in addressing contiguous memory locations in said first and second portions of said memory means, address demultiplexing means coupled to said processing means and adapted to provide memory addresses, a first multiplexer responsive to row and column strobe signals provided by said processing means, a second multiplexer responsive to said mode control signals, said first and second multiplexers coupled to said address demultiplexing means and adapted, in response to the generation of said first ode control signal, to selectively provide first address signals adapted to access said first portion of said memory means in response to the generation of said second mode control signal, to selectively provide second address signals adapted to access said second portion of said memory means, said first address signals including a first row address portion and a first column address portion, said second address signals including a second row address portion and a second column address portion, wherein the first predetermined bit positions of said second column address portion are constrained to be of a preselected value and wherein said second row address portion includes second predetermined bit positions corresponding in position in said memory addresses to said first predetermined bit positions, said first multiplexer including a plurality of first switching devices and a plurality of second switching devices wherein selected ones of said plurality of second switching devices have respective terminals thereof coupled to a predetermined reference potential and said second multiplexer includes a plurality of third switching devices having respective terminals thereof coupled to respective terminals of said first and second switching devices.