§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0241288A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Microprocessor video display system

Assignee: Amstrad PLC
•
Filing: 1987-04-09
•
Granted: —
•
Expires: 2007-04-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a microprocessor video display system a pixel-mapped video memory (10) can be accessed both by the CPU (12) and by video display logic (14) which delivers video data to the display. Contrary to accepted practice, contention between simultaneous access requests from the CPU and video display logic is avoided by the video display logic deferring its access request for one video memory access period. This is acceptable because: the video control logic can access data at a rate twice that required by the display, the video memory access cycle rate is the same as the CPU clock rate, and the microprocessor accesses the memory for one clock period during operation cycles lasting three orfourclock pulses. The CPU operation is thus kept at its maximum speed without the video data being adversely delayed.

Inventors

  • 👤 John Flare Technology Mathieson

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 00:10
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/001

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 135 words
A microprocessor video display system comprising a video memory, a CPU capable of accessing the video memory for one clock period during operation cycles each lasting two or more CPU clock periods, video control logic for accessing the video memory during selected video memory read cycles to provide data to a video display device, the video control logic being capable of accessing the video memory at a rate twice as fast as the rate at which data is required to be delivered to the video display device, and the video memory read cycle rate being substantially equal to the CPU clock rate, and in which when both the CPU and the video display device desire access to the video memory the operation of the video control logic is deferred by one video memory access period.
Claim 2
Dependent Claim 135 words
A microprocessor video display system comprising a video memory, a CPU capable of accessing the video memory for one clock period during operation cycles each lasting two or more CPU clock periods, video control logic for accessing the video memory during selected video memory read cycles to provide data to a video display device, the video control logic being capable of accessing the video memory at a rate twice as fast as the rate at which data is required to be delivered to the video display device, and the video memory read cycle rate being substantially equal to the CPU clock rate, and in which when both the CPU and the video display device desire access to the video memory the operation of the video control logic is deferred by one video memory access period.
Claim 3
Dependent Claim 19 words
A microprocessor video display system according to claim 1, in which the CPU is comprised by a Z80 microprocessor.
Claim 4
Dependent Claim 21 words
A microprocessor video display system according to claim 1 or 2 in which the video memory is a pixel-mapped video memory.
Claim 5
Dependent Claim 21 words
A microprocessor video display system substantially as herein described with reference to and as shown in Figure 2 of the drawing.
Claim 6
Dependent Claim 21 words
A microprocessor video display system substantially as herein described with reference to and as shown in Figure 2 of the drawing.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag