IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors

Claim 1

An integrated digital electronic circuit chip, comprising: a plurality of volatile memory cells having at least one non-adjacent volatile memory cell which is laid out on an active surface of said chip in such a manner that said non-adjacent volatile memory cell is not adjacent to any other of said plurality of volatile memory cells, a plurality of non-volatile memory cells, equal in number to said plurality of volatile memory cells, each of said non-volatile memory cells being uniquely associated with one of said plurality of volatile memory cells to form a memory cell pair and programmed with an initial value for said associated volatile memory cell, and means connected to each of said memory cell pairs for simultaneously loading said initial values from said plurality of non-volatile memory cells into said plurality of volatile memory cells; wherein said loading means includes a plurality of switching transistors, each of said plurality of switching transistors having an individual control element and being connected to one of said memory cell pairs, and said individual control elements of said plurality of switching transistors being connected together in such a manner as to permit simultaneous loading of said plurality of volatile memory cells with their initial values.