US4646269A
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Multiple programmable initialize words in a programmable read only memory
Assignee: Lattice Semiconductor Corp
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Filing: 1984-09-18
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Granted: 1987-02-24
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Expires: 2004-09-18
Abstract
Abstract A programmable read-only memory (40) is provided which is capable of storing a plurality of initialize words. The memory includes an initialize input lead (9) and appropriate addressing circuitry (7) so that when the appropriate initialize input signal is placed on the initialize input lead, one of several pre-programmed initialize words is placed in the output register (6) of the programmable read-only memory. The word that is placed in the output register is selected according to signals applied to selected address input leads (A 0 through A 3 ) of the programmable read-only memory. The number of address input signals utilized to determine which initialize word is placed in the output register of the programmable read-only memory is a selected subset of the available address input signals provided to the memory. The described embodiment provides sixteen initialize words using a minimum number of components. The sixteen initialize words are stored in an additional row (12) of the programmable array which contains the memory's normally addressable data words. Because the initialize word circuit (12) is configured as an extra row of the programmable array, the initialize word occupies less chip area than a conventional initialize word circuit. In addition, fewer components are necessary to implement the initialize word circuit of this invention because the inherent selection circuitry of the programmable array is used rather than circuitry which deselects the normal data word provided by the programmable array.
Inventors
- 👤 Sing Y. Wong
- 👤 Johnny Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:52
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20; G11C17/00; G11C17/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having K initialize input terminals, where K is a positive integer, comprising: means for storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words where L is an integer greater than one, said means having K initialize input leads each connected to an associated one of said initialize input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input leads.
Claim 2
Dependent Claim
149 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having K initialize input terminals, where K is a positive integer, comprising: means for storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words where L is an integer greater than one, said means having K initialize input leads each connected to an associated one of said initialize input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input leads.
Claim 3
Dependent Claim
167 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having an initialize input terminal, comprising: means for storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words where L is an integer greater than one, said means having an initialize input lead connected to said initialize input terminal, and K address input leads, where K is a positive integer less than or equal to N, connected to selected address input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input lead and said K initialize input leads.
Claim 4
Dependent Claim
167 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having an initialize input terminal, comprising: means for storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words where L is an integer greater than one, said means having an initialize input lead connected to said initialize input terminal, and K address input leads, where K is a positive integer less than or equal to N, connected to selected address input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input lead and said K initialize input leads.
Claim 5
Dependent Claim
154 words
A read only memory circuit (ROM) having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having K initialize input terminals, where K is a positive integer, comprising: means for nondestructively storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words, where L is a positive integer greater than one, said means having K initialize input leads each connected to an associated one of said initialize input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input leads.
Claim 6
Dependent Claim
154 words
A read only memory circuit (ROM) having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having K initialize input terminals, where K is a positive integer, comprising: means for nondestructively storing X M-bit data words, where X is a positive integer, wherein said means for storing provides an M-bit data word on said data output terminals in response to said address input signals; and means for providing L initialize data output words, where L is a positive integer greater than one, said means having K initialize input leads each connected to an associated one of said initialize input terminals, wherein said means provides one of said L initialize output words on said data output terminals in response to signals received on said initialize input leads.
Claim 7
Dependent Claim
314 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having an initialize input terminal, comprising: a first decoder having L input leads, where L is a positive integer less than N, connected to selected ones of said address input terminals, and having K output leads, where K is a positive integer; a programmable logic array having K input leads, each connected to an associated one of said output leads of said first decoder and having I output leads, where I in an integral multiple of M; a second decoder having H input leads, where H is a positive integer less than N, connected to selected ones of said address input terminals, and having G output leads, where G is a positive integer; a programmable initialize word circuit having an initialize input lead connected to said initialize input terminal, having I input leads, each input lead connected to an associated one of said output leads of said programmable logic array, and having I output leads, wherein, when an initialize input signal is received on said initialize input lead, said programmable initialize word circuit provides a preprogrammed set of I output signals on said output leads, and wherein, when said initialize input lead does not receive said initialize input signal said programmable initialize word circuit provides the signals received on said input leads on said output leads; a multiplexer having G address input leads, each connected to an associated one of said output leads of said second decoder, having I input leads, each connected to an associated one of said output leads of said programmable initialize word circuit, and having M output leads, each connected to an associated one of said data output terminals.
Claim 8
Dependent Claim
314 words
A memory circuit having a plurality of N address input terminals, where N is a positive integer, for receiving address input signals, having M data output terminals, where M is a positive integer, for providing M bit data output words, and having an initialize input terminal, comprising: a first decoder having L input leads, where L is a positive integer less than N, connected to selected ones of said address input terminals, and having K output leads, where K is a positive integer; a programmable logic array having K input leads, each connected to an associated one of said output leads of said first decoder and having I output leads, where I in an integral multiple of M; a second decoder having H input leads, where H is a positive integer less than N, connected to selected ones of said address input terminals, and having G output leads, where G is a positive integer; a programmable initialize word circuit having an initialize input lead connected to said initialize input terminal, having I input leads, each input lead connected to an associated one of said output leads of said programmable logic array, and having I output leads, wherein, when an initialize input signal is received on said initialize input lead, said programmable initialize word circuit provides a preprogrammed set of I output signals on said output leads, and wherein, when said initialize input lead does not receive said initialize input signal said programmable initialize word circuit provides the signals received on said input leads on said output leads; a multiplexer having G address input leads, each connected to an associated one of said output leads of said second decoder, having I input leads, each connected to an associated one of said output leads of said programmable initialize word circuit, and having M output leads, each connected to an associated one of said data output terminals.
References Cited (Backward Citations)
US4281398A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |