Abstract An information terminal apparatus has a capability of continuously operating, when a battery capacity drop is detected, and maintaining the battery capacity at a certain level for an extended period. When the battery capacity drops to cause a battery voltage generating circuit to generate a warning signal, a clock frequency switching circuit switches a clock signal from a normal frequency to a lower frequency, whereby the apparatus operates at a speed slower than before and accordingly consumes less current, so that even if the apparatus keeps operating, a time period available until it eventually stops can be prolonged. Therefore, a user can definitely recognize deterioration of the performance of the apparatus or slow-down of the operating speed due to a battery capacity drop. Also, since a time period available until the apparatus stops is longer, countermeasures such as exchanging or recharging the battery can be readily taken before the battery is completely used up.
An information terminal apparatus, comprising: a CPU; at least one peripheral device; a battery supplying voltage to said CPU and said at least one peripheral device; a first battery voltage detecting circuit for detecting a voltage level of said battery and outputting a warning signal to said CPU when said voltage level is less than a first threshold; a second battery voltage detecting circuit for detecting a voltage level of said battery and outputting a halt signal to said CPU when said voltage level is less than a second threshold, whereby operations of said CPU and said at least one peripheral device are halted in response to said halt signal; and a clock frequency switching circuit, operatively associated with said CPU, for supplying a high frequency clock signal to said CPU when said warning signal is not being outputted, and switching said CPU to a lower frequency clock signal when said warning signal is being outputted.
Claim 2
Dependent Claim
156 words
An information terminal apparatus, comprising: a CPU; at least one peripheral device; a battery supplying voltage to said CPU and said at least one peripheral device; a first battery voltage detecting circuit for detecting a voltage level of said battery and outputting a warning signal to said CPU when said voltage level is less than a first threshold; a second battery voltage detecting circuit for detecting a voltage level of said battery and outputting a halt signal to said CPU when said voltage level is less than a second threshold, whereby operations of said CPU and said at least one peripheral device are halted in response to said halt signal; and a clock frequency switching circuit, operatively associated with said CPU, for supplying a high frequency clock signal to said CPU when said warning signal is not being outputted, and switching said CPU to a lower frequency clock signal when said warning signal is being outputted.