Solid state imaging apparatus with large electric charge amount in vertical transfer

Claim 2

A solid state imaging apparatus comprising: a solid state imager of an interline charge transfer device type including a number of photoelectric conversion cells arranged in the form of matrix, a plurality of vertical transfer registers each of which is arranged to extend adjacent to and along a corresponding one column of photoelectric conversion cells, reading means provided between each one column of photoelectric conversion cells and one adjacent vertical transfer register for reading and transferring an electric charge stored in each one of N photoelectric conversion cells to said adjacent vertical transfer register (where N is natural number not less than 2), a horizontal transfer register located at output ends of all the vertical transfer registers, and an output amplifier located at an output of the horizontal transfer register, said reading means performing said transferring of the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register N times in such a manner that each of N transferrings is made for a different one of each N photoelectric conversion cells; a memory receiving an image signal sequentially outputted from said solid state imager and having a capacity corresponding to a double of the number of the photoelectric conversion cells of said solid state imager; and a control circuit connected to said memory and to said solid state imager for controlling driving of said solid state imager and said memory such that after said transferrings have been performed N times an image signal for one image detected by all said photoelectric conversion cells of said solid state imager is stored into a first half of said memory and said image signal is read out from said first half of said memory in accordance with a desired television format, and concurrently, said reading means transfers the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register so that an image signal for a next one image detected by said photoelectric conversion cells of said solid state imager is stored into a second half of said memory.

Claim 3

A solid state imaging apparatus claimed in claim 1 wherein N is not less than 3.

Claim 4

A solid state imaging apparatus claimed in claim 1 wherein N is an even number not less than 4.

Claim 5

A solid state imaging apparatus comprising: a solid state imager of an interline charge transfer device type including a number of photoelectric conversion cells arranged in the form of matrix, a plurality of vertical transfer registers each of which is arranged to extend adjacent to and along a corresponding one column of photoelectric conversation cells, reading means provided between each one column of photoelectric conversion cells and one adjacent vertical transfer register for reading and transferring an electric charge stored in each one of each N photoelectric conversion cells to said adjacent vertical transfer register (where N is natural number not less than 2), a horizontal transfer register located at output ends of all the vertical transfer registers, and an output amplifier located at an output of the horizontal transfer register, said reading means performing said transferring of the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register N times in such a manner that each of N transferrings is made for a different one of each N photoelectric conversion cells; a memory receiving an image signal sequentially outputted from said solid state imager and having a capacity corresponding to a double of the number of the photoelectric conversion cells of said solid state imager; and a control circuit connected to said memory and to said solid state imager for controlling driving of said solid state imager and said memory such that after said transferrings have been performed N times in said manner, an image signal for one image detected by all said photoelectric conversion cells of said solid state imager is stored into a first half of said memory and said image signal is read out from said first half of said memory in accordance with a desired television format, and concurrently, said reading means transfers the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register so that an image signal for a next one image detected by said photoelectric conversion cells of said solid state imager is stored into a second half of said memory, wherein said reading means includes a reading gate provided between each of photoelectric conversion cells in each one column and one adjacent vertical transfer register so as to transfer an electric charge stored in each photoelectric conversion cell into said one adjacent vertical transfer register, said reading gate being selectively opened by said control circuit so that an electric charge stored in only a selected one of N photoelectric conversion cells is transferred to said adjacent vertical transfer register.

Claim 6

A solid state imaging apparatus comprising: a solid state imager of an interline charge transfer device type including a number of photoelectric conversion cells arranged in the form of matrix, a plurality of vertical transfer registers each of which is arranged to extend adjacent to and along a corresponding one column of photoelectric conversation cells, reading means provided between each one column of photoelectric conversion cells and one adjacent vertical transfer register for reading and transferring an electric charge stored in each one of each N photoelectric conversion cells to said adjacent vertical transfer register (where N is natural number not less than 2), a horizontal transfer register located at output ends of all the vertical transfer registers, and an output amplifier located at an output of the horizontal transfer register, said reading means performing said transferring of the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register N times in such a manner that each of N transferrings is made for a different one of each N photoelectric conversion cells; a memory receiving an image signal sequentially outputted from said solid state imager and having a capacity corresponding to a double of the number of the photoelectric conversion cells of said solid state imager; and a control circuit connected to said memory and to said solid state imager for controlling driving of said solid state imager and said memory such that after said transferrings have been performed N times in said manner, an image signal for one image detected by all said photoelectric conversion cells of said solid state imager is stored into a first half of said memory and said image signal is read out from said first half of said memory in accordance with a desired television format, and concurrently, said reading means transfers the electric charge stored in one of each N photoelectric conversion cells to said adjacent vertical transfer register so that an image signal for a next one image detected by said photoelectric conversion cells of said solid state imager is stored into a second half of said memory, wherein said reading means includes a reading gate provided between each of photoelectric conversion cells in each one column and one adjacent vertical transfer register so as to transfer an electric charge stored in each photoelectric conversion cell into said one adjacent vertical transfer register, said reading gate being selectively opened by said control circuit so that an electric charge stored in only a selected one of N photoelectric conversion cells is transferred to said adjacent vertical transfer register.

Claim 7

A solid state imaging apparatus claimed in claim 4 wherein N is not less than 3.

Claim 8

A solid state imaging apparatus claimed in claim 4 wherein N is an even number not less than 4.