US4839739A
Expired / Lapsed
US
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Image signal binary circuit with a variable-frequency clock signal generator for driving an image sensor
Assignee: Hitachi Ltd
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Filing: 1987-03-09
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Granted: 1989-06-13
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Expires: 2007-03-09
Abstract
Abstract A one-dimensional image sensor comprising a solid image pick-up element takes images in sequence, and generates an image signal. Clock pulses from a frequency variable type clock pulse generator having a frequency which varies in correspondence to a control signal are supplied to a one-dimensional image sensor, thereby image signals are outputted in sequence. The image signal is amplified by an amplifier and inputted to a comparator and compared with a reference signal. A frequency variable range of the frequency variable type clock pulse generator is set higher than the cut-off frequency of the amplifier, and the binary level output by the comparator is substantially the same as the image inputted to the one-dimensional image sensor and control is effected by the variable frequency of the clock pulses.
Inventors
- 👤 Tsuguji Tachiuchi
- 👤 Satoshi Konuma
- 👤 Nobuo Tsuchiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:51
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/403; H04N1/40056
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
102 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; and comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; wherein the signal level of one of said image signal from said image sensor and said reference signal is varied in accordance with the frequency of said generated clock signal.
Claim 2
Dependent Claim
102 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; and comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; wherein the signal level of one of said image signal from said image sensor and said reference signal is varied in accordance with the frequency of said generated clock signal.
Claim 3
Dependent Claim
34 words
An image signal binary circuit according to calim 1, wherein an image of a specific color component is inputted to said image sensor, and said control signal varies according to said specific color component.
Claim 4
Dependent Claim
34 words
An image signal binary circuit according to calim 1, wherein an image of a specific color component is inputted to said image sensor, and said control signal varies according to said specific color component.
Claim 5
Dependent Claim
112 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; and amplifying means connected between said image sensor and said comparing means for amplifying said image signal; wherein the frequency variation range of said clock signal generating means is set to a region exceeding the cut-off frequency of said amplifying means.
Claim 6
Dependent Claim
112 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; and amplifying means connected between said image sensor and said comparing means for amplifying said image signal; wherein the frequency variation range of said clock signal generating means is set to a region exceeding the cut-off frequency of said amplifying means.
Claim 7
Dependent Claim
117 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; and amplifying means connected between said image sensor and said comparing means for amplifying said image signal; wherein the cut-off frequency of said amplifying means is set to a frequency lower than the maximum frequency in the frequency variation range of said clock signal generating means.
Claim 8
Dependent Claim
117 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; and amplifying means connected between said image sensor and said comparing means for amplifying said image signal; wherein the cut-off frequency of said amplifying means is set to a frequency lower than the maximum frequency in the frequency variation range of said clock signal generating means.
Claim 9
Dependent Claim
181 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; amplifying means for amplifying said image signal from said image sensor and for supplying the amplified image signal to said comparing means; and reference signal generating means for generating said reference signal and for supplying it to said comparing means; wherein said reference signal generating means comprises peak hold means for detecting and holding the peak value of the amplified image signal, and dividing means for dividing an output of said peak hold means to generate said reference signal; and wherein the cut-off frequency of said peak hold means is set to a frequency lower than the maximum frequency in the frequency variation range of said clock signal generating means.
Claim 10
Dependent Claim
181 words
An image signal binary circuit, comprising: clock signal generating means for varying the frequency of a generated clock signal in response to a control signal; an image sensor for converting an object into an electric image signal and for outputting said image signal in synchronization with said clock signal; comparing means for comparing said image signal from said image sensor with a reference signal and for outputting a binary image signal; amplifying means for amplifying said image signal from said image sensor and for supplying the amplified image signal to said comparing means; and reference signal generating means for generating said reference signal and for supplying it to said comparing means; wherein said reference signal generating means comprises peak hold means for detecting and holding the peak value of the amplified image signal, and dividing means for dividing an output of said peak hold means to generate said reference signal; and wherein the cut-off frequency of said peak hold means is set to a frequency lower than the maximum frequency in the frequency variation range of said clock signal generating means.
Claim 11
Dependent Claim
102 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; and comparing means for comparing the image signal with said reference signal and for outputting a binary image signal; wherein the signal level of one of said image and reference signals inputted to said comparing means is varied in accordance with the frequency of said clock signal.
Claim 12
Dependent Claim
102 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; and comparing means for comparing the image signal with said reference signal and for outputting a binary image signal; wherein the signal level of one of said image and reference signals inputted to said comparing means is varied in accordance with the frequency of said clock signal.
Claim 13
Dependent Claim
28 words
An image signal binary device according to claim 6, wherein a specific color component of the object is inputted to a light receiving member of said converting means.
Claim 14
Dependent Claim
121 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means and for supplying the amplified image signal to said comparing means; wherein the frequency variation range of said frequency variable type clock signal generating means is set higher than the cut-off frequency of said amplifying means.
Claim 15
Dependent Claim
121 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means and for supplying the amplified image signal to said comparing means; wherein the frequency variation range of said frequency variable type clock signal generating means is set higher than the cut-off frequency of said amplifying means.
Claim 16
Dependent Claim
157 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means for supplying the amplified image signal to said comparing means; wherein said reference signal generating means comprises peak hold means for receiving said amplified image signal and for detecting and holding the peak value thereof; and wherein the frequency variation range of said frequency variable type clock signal generating means is set lower than the cut-off frequency of said amplifying means and higher than the cut-off frequency of said peak hold means.
Claim 17
Dependent Claim
157 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means for supplying the amplified image signal to said comparing means; wherein said reference signal generating means comprises peak hold means for receiving said amplified image signal and for detecting and holding the peak value thereof; and wherein the frequency variation range of said frequency variable type clock signal generating means is set lower than the cut-off frequency of said amplifying means and higher than the cut-off frequency of said peak hold means.
Claim 18
Dependent Claim
125 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; color separating means installed on a light receiving member of said converting means for separating a selected one of a plurality of color components from the object and for introducing the selected color component to said light receiving member; and means for generating said control signal according to the selected color component.
Claim 19
Dependent Claim
125 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; color separating means installed on a light receiving member of said converting means for separating a selected one of a plurality of color components from the object and for introducing the selected color component to said light receiving member; and means for generating said control signal according to the selected color component.
Claim 20
Dependent Claim
58 words
An image signal binary device, according to claim 10, further comprising: amplifying means for amplifying said image signal from said converting means and for supplying the amplified image signal to said comparing means; wherein the frequency variation range of said frequency variable type clock signal generating means is set higher than the cut-off frequency of said amplifying means.
Claim 21
Dependent Claim
71 words
An image signal binary device according to claim 11, wherein said reference signal generating means comprises peak hold means for receiving said amplified image signal and for detecting and holding the peak value thereof; and wherein the frequency variation range of said frequency variable type clock signal generating means is set lower than the cut-off frequency of said amplifying means and higher than the cut-off frequency of said peak hold means.
Claim 22
Dependent Claim
39 words
An image signal binary device according to claim 11, wherein said reference signal generating means further comprises dividing means connected to said peak hold means for dividing an output of said peak hold means to generate said reference signal.
Claim 23
Dependent Claim
141 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means and for supplying the amplified image signal to said comparing means; wherein a specific color component of the object is inputted to a light receiving member of said converting means; and wherein the frequency variation range of said frequency variable type clock signal generating means is set higher than the cut-off frequency of said amplifying means.
Claim 24
Dependent Claim
141 words
An image signal binary device, comprising: frequency variable type clock signal generating means for generating a clock signal of a prescribed frequency in response to a control signal; means for converting an object into an image signal and for outputting said image signal in synchronization with said clock signal; means for generating a reference signal; comparing means for comparing said image signal with said reference signal and for outputting a binary image signal; and amplifying means for amplifying said image signal from said converting means and for supplying the amplified image signal to said comparing means; wherein a specific color component of the object is inputted to a light receiving member of said converting means; and wherein the frequency variation range of said frequency variable type clock signal generating means is set higher than the cut-off frequency of said amplifying means.
Claim 25
Dependent Claim
114 words
An image signal input device, comprising: an image sensor; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying an image signal outputted from said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein a signal amplitude of one of said image and reference signals applied to said comparing means is varied in accordance with the frequency of said clock signal.
Claim 26
Dependent Claim
114 words
An image signal input device, comprising: an image sensor; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying an image signal outputted from said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein a signal amplitude of one of said image and reference signals applied to said comparing means is varied in accordance with the frequency of said clock signal.
Claim 27
Dependent Claim
22 words
An image signal input device according to claim 15, wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element.
Claim 28
Dependent Claim
158 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein said clock signal generating means comprises oscillating means, frequency dividing means for dividing an output of said oscillating means, decoder means for decoding said control signal, and a logic circuit for receiving an output of said frequency dividing means and an output of said decoder means and for generating said clock signal.
Claim 29
Dependent Claim
158 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein said clock signal generating means comprises oscillating means, frequency dividing means for dividing an output of said oscillating means, decoder means for decoding said control signal, and a logic circuit for receiving an output of said frequency dividing means and an output of said decoder means and for generating said clock signal.
Claim 30
Dependent Claim
142 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein the frequency variation range of said clock signal is set to a frequency range such that the gain of said amplifying means varies at a prescribed rate in accordance with the frequency of said clock signal.
Claim 31
Dependent Claim
142 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein the frequency variation range of said clock signal is set to a frequency range such that the gain of said amplifying means varies at a prescribed rate in accordance with the frequency of said clock signal.
Claim 32
Dependent Claim
130 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein the frequency variation range of said clock signal is set to a frequency range such that the gain of said amplifying means is constant.
Claim 33
Dependent Claim
130 words
An image signal input device, comprising: an image sensor for generating an image signal; clock signal generating means for generating a clock signal to drive said image sensor, said clock signal generating means having a control terminal, the frequency of said clock signal being varied in accordance with a control signal inputted to said control terminal; amplifying means for amplifying said image signal generated by said image sensor; a reference signal generating circuit for generating a reference signal; and comparing means for comparing the amplified image signal with said reference signal; wherein said image sensor comprises at least a one-dimensional solid-state image pick-up element; and wherein the frequency variation range of said clock signal is set to a frequency range such that the gain of said amplifying means is constant.
Claim 34
Dependent Claim
63 words
An image signal input device according to claim 19, wherein said reference signal generating circuit comprises a circuit for peak-holding the amplified image signal, and wherein the frequency variation range of said clock signal is set to a frequency range such that a frequency characteristic of said peak-holding circuit varies at a prescribed rate in accordance with the frequency of said clock signal.
References Cited (Backward Citations)
US4159488A
Cited
US4521804A
Cited
US4673972A
Cited
JPS60123158A
Cited
JPS60158769A
Cited
JPS60176360A
Cited
US4598322A
Cited
JPH0641371A
Cited
USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
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