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US5229625A Expired / Lapsed US ⏱️ 0.0 years remaining

Schottky barrier gate type field effect transistor

Assignee: Sharp Corp
•
Filing: 1991-09-25
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Granted: 1993-07-20
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Expires: 2011-09-25
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Abstract

Abstract The semiconductor device somprises a silicon substrate, a boron-doped high resistant silicon carbide layer formed on said silicon substrate and a silicon carbide layer formed on said high resistant silicon carbide layer.

Inventors

  • 👤 Akira Suzuki
  • 👤 Katsuki Furukawa
  • 👤 Akitsugu Hatano
  • 👤 Atsuko Uemoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 02:03
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10D1/00; H10D1/60; H10D1/68; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H10W70/698

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 164 words
A structure for a Schottky-barrier gate type FET semiconductor device comprising: a single crystal silicon substrate; a first high resistant single crystal silicon carbide layer being boron-doped and disposed on said single crystal silicon substrate, said first high resistant single crystal silicon carbide layer comprising a resistivity of greater than 100 Ωcm; a second silicon carbide layer disposed on said first high resistant single crystal silicon carbide layer for forming an active layer of the semiconductor device, wherein said second silicon carbide layer is electrically insulated from said single crystal silicon substrate by said first high resistant single crystal silicon carbide layer; a first electrode layer disposed on a first portion of said second silicon carbide layer; a source electrode formed from a first portion of said first electrode layer; a drain electrode formed from a second portion of said first electrode layer; and a second electrode layer disposed on a second portion of said second silicon carbide layer for forming a gate electrode.
Claim 2
Dependent Claim 164 words
A structure for a Schottky-barrier gate type FET semiconductor device comprising: a single crystal silicon substrate; a first high resistant single crystal silicon carbide layer being boron-doped and disposed on said single crystal silicon substrate, said first high resistant single crystal silicon carbide layer comprising a resistivity of greater than 100 Ωcm; a second silicon carbide layer disposed on said first high resistant single crystal silicon carbide layer for forming an active layer of the semiconductor device, wherein said second silicon carbide layer is electrically insulated from said single crystal silicon substrate by said first high resistant single crystal silicon carbide layer; a first electrode layer disposed on a first portion of said second silicon carbide layer; a source electrode formed from a first portion of said first electrode layer; a drain electrode formed from a second portion of said first electrode layer; and a second electrode layer disposed on a second portion of said second silicon carbide layer for forming a gate electrode.
Claim 3
Dependent Claim 15 words
A structure as set forth in claim 1, wherein said first electrode layer comprises Ni.
Claim 4
Dependent Claim 15 words
A structure as set forth in claim 1, wherein said second electrode layer comprises Au.
Claim 5
Dependent Claim 20 words
A structure as set forth in claim 1, wherein said second silicon carbide layer comprises n-type single crystal silicon carbide.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-07-19 1997-01-18 1997-07-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-07-19 2001-01-18 2001-07-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-07-19 2005-01-18 2005-07-20 $7700.00 Window Closed / Lapsed

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