US5227961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetrical delay circuit
Assignee: General Electric Co
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Filing: 1991-12-20
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Granted: 1993-07-13
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Expires: 2011-12-20
Abstract
Abstract Dead time circuitry for ensuring that no two switching devices in a half-bridge, or in the same leg of a full-bridge, are conductive simultaneously employs a symmetrical delay circuit which independently delays the rising and falling edges of each signal pulse.
Inventors
- 👤 Glenn S. Claydon
- 👤 William J. Laughton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:27
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/337; H02M3/3376; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
145 words
A symmetrical delay circuit for independently delaying the rising and falling edges of an input digital data signal, comprising: input latching means for latching the rising and falling edges, respectively, of said digital data signal; turn-on delay means responsive to said input latching means for delaying said rising edges of said digital data signal, said turn-on delay means including a first capacitor for current-controlled charging to a predetermined level; turn-off delay means responsive to said input latching means for delaying said falling edges of said digital data signal, said turn-off delay means including a second capacitor for current-controlled charging to said predetermined level; a current mirror circuit for providing a controlled current for charging said first and second capacitors to said predetermined level; and output latching means for providing as an output signal the delayed rising and falling edges of said digital data signal, respectively.
Claim 2
Dependent Claim
145 words
A symmetrical delay circuit for independently delaying the rising and falling edges of an input digital data signal, comprising: input latching means for latching the rising and falling edges, respectively, of said digital data signal; turn-on delay means responsive to said input latching means for delaying said rising edges of said digital data signal, said turn-on delay means including a first capacitor for current-controlled charging to a predetermined level; turn-off delay means responsive to said input latching means for delaying said falling edges of said digital data signal, said turn-off delay means including a second capacitor for current-controlled charging to said predetermined level; a current mirror circuit for providing a controlled current for charging said first and second capacitors to said predetermined level; and output latching means for providing as an output signal the delayed rising and falling edges of said digital data signal, respectively.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-12 | 1997-01-11 | 1997-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-12 | 2001-01-11 | 2001-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-12 | 2005-01-11 | 2005-07-13 | $7700.00 | Window Closed / Lapsed |