Semiconductor device

Claim 2

A semiconductor device comprising: a single crystal semiconductor substrate; a polycrystalline semiconductor region, having a low resistance, disposed to overlie a surface of said semiconductor substrate; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, said single crystal semiconductor region comprising a first region of a first conductivity type, a second region of a second conductivity type and a third region of said first conductivity type disposed one under another downward from a surface thereof, wherein the surface of said substrate is a (111) plane.

Claim 3

A semiconductor device according to claim 1, wherein a semiconductor layer having a low resistance is disposed between said polycrystalline semiconductor region and said single crystal semiconductor region and/or said semiconductor substrate.

Claim 4

A semiconductor device according to claim 1, wherein said polycrystalline semiconductor region is comprised of a first portion extending in a lateral direction, parallel to the substrate surface, and a second portion, contiguous to said first portion, extending in an orthogonal direction to said first portion and toward the substrate surface.

Claim 5

A semiconductor device according to claim 3, wherein the second portion of said polycrystalline semiconductor region and said single crystal semiconductor region are insulated from each other by a thick insulating layer.

Claim 6

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein the surface of said substrate is a (111) plane.

Claim 7

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein the surface of said substrate is a (111) plane.

Claim 8

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein said polycrystalline semiconductor region is comprised of a first portion extending in a lateral direction, parallel to the substrate surface, and a second portion, contiguous to said first portion, extending in an orthogonal direction to said first portion and toward the substrate surface.

Claim 9

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein said polycrystalline semiconductor region is comprised of a first portion extending in a lateral direction, parallel to the substrate surface, and a second portion, contiguous to said first portion, extending in an orthogonal direction to said first portion and toward the substrate surface.

Claim 10

A semiconductor device according to claim 6, wherein the second portion of said polycrystalline semiconductor region and said single crystal semiconductor region are insulated from each other by a thick insulating layer.

Claim 11

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein said single crystal semiconductor region comprises a first layer of first conductivity type, a second layer of second conductivity type and a third layer of first conductivity type disposed one under another downward from a surface thereof, said third layer being electrically connected to said polycrystalline semiconductor region.

Claim 12

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein said single crystal semiconductor region comprises a first layer of first conductivity type, a second layer of second conductivity type and a third layer of first conductivity type disposed one under another downward from a surface thereof, said third layer being electrically connected to said polycrystalline semiconductor region.

Claim 13

A semiconductor memory device comprising a single crystal semiconductor substrate; a first insulating layer being disposed on a surface of said semiconductor substrate; a polycrystalline or amorphous semiconductor region being disposed on said first insulating layer; a second insulating layer being disposed on said polycrystalline or amorphous semiconductor region; a single crystal semiconductor region being disposed on said second insulating layer; and a first layer of a first conductivity type, a second layer of a second conductivity type and a third layer of said first conductivity type being formed in said single crystal semiconductor region and being disposed one under another downward from a surface of said single crystal semiconductor region toward said first insulating layer, these first, second and third layers together consisting a transistor, said third layer together with said polycrystalline or amorphous semiconductor region and said second insulating layer disposed therebetween comprise a capacitor.

Claim 14

A semiconductor memory device comprising a single crystal semiconductor substrate; a first insulating layer being disposed on a surface of said semiconductor substrate; a polycrystalline or amorphous semiconductor region being disposed on said first insulating layer; a second insulating layer being disposed on said polycrystalline or amorphous semiconductor region; a single crystal semiconductor region being disposed on said second insulating layer; and a first layer of a first conductivity type, a second layer of a second conductivity type and a third layer of said first conductivity type being formed in said single crystal semiconductor region and being disposed one under another downward from a surface of said single crystal semiconductor region toward said first insulating layer, these first, second and third layers together consisting a transistor, said third layer together with said polycrystalline or amorphous semiconductor region and said second insulating layer disposed therebetween comprise a capacitor.

Claim 15

A semiconductor device according to claim 9, wherein the surface of said substrate is a (111) plane.

Claim 16

A semiconductor device according to claim 8, wherein said first layer, said second layer and said third layer are an emitter, a base and a collector of a bipolar transistor, respectively.

Claim 17

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein a silicide layer is formed on said single crystal semiconductor region, and wherein together said silicide layer and said single crystal semiconductor region form a Schottky barrier type diode.

Claim 18

A semiconductor device comprising: a single crystal semiconductor substrate; an insulating region being disposed on a surface of said single crystal semiconductor substrate; a polycrystalline semiconductor region having a low resistance and being disposed on said insulating region; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, wherein a silicide layer is formed on said single crystal semiconductor region, and wherein together said silicide layer and said single crystal semiconductor region form a Schottky barrier type diode.

Claim 19

A semiconductor device comprising: a single crystal semiconductor substrate; a polycrystalline semiconductor region, having a low resistivity, disposed to overlie a surface of said semiconductor substrate; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, said single crystal semiconductor region comprising a first region of a first conductivity type, a second region of a second conductivity type and a third region of said first conductivity type disposed one under another downward from a surface thereof, wherein said polycrystalline semiconductor region is disposed directly on the surface of said single crystal semiconductor substrate, and wherein at the surface of said single crystal semiconductor substrate there is included, as a surface region thereof, a thin low resistance semiconductor layer.

Claim 20

A semiconductor device comprising: a single crystal semiconductor substrate; a polycrystalline semiconductor region, having a low resistivity, disposed to overlie a surface of said semiconductor substrate; and a single crystal semiconductor region being disposed to directly overlie said polycrystalline semiconductor region, said single crystal semiconductor region comprising a first region of a first conductivity type, a second region of a second conductivity type and a third region of said first conductivity type disposed one under another downward from a surface thereof, wherein said polycrystalline semiconductor region is disposed directly on the surface of said single crystal semiconductor substrate, and wherein at the surface of said single crystal semiconductor substrate there is included, as a surface region thereof, a thin low resistance semiconductor layer.

Claim 21

A semiconductor device according to claim 13, wherein said thin low resistance semiconductor layer is a heavily doped diffusion layer.