Parallel operation processor with second command unit

Claim 1

A parallel operation processor, comprising: a first integer unit connected to a bus for performing integer or logic operations and generating a carry signal; a first command unit connected to said bus for access to said first integer unit through said bus and pipelining fetch, decode, and transfer of a first command to said first integer unit; a second integer unit connected to said bus and being identical with said first integer unit in terms of function; f a second command unit connected to said bus for access to said second integer unit to transfer a second command to said second integer unit and receive a control command from said first command unit through a control bus, and being identical with said first command unit in terms of function; a carry bit connected to said first and second integer units, into which a carry signal is selectively inputted by said first and second integer units for holding a carry resulting from an operation performed by said first and second integer units; a program counter connected said first and second command units, for feeding said first and second command units with a first address of said first command and a second address of said second command, respectively, and incrementing address values; a data unit connected to said bus to permit selective data write or read by said first and second command units; register file consisting of a plurality of registers connected to said bus and being accessed by said first and second integer units and said first and second command units to read and write data for performing arithmetic and logic and operations; and a priority score board connected to said register file and having a plurality of score bits each corresponding to each of said registers of said register file and being set during use of a corresponding register by any one of said integer units and said command units.