Method for selectively transferring data instructions to a cache memory

Claim 1

In a data processing system including a central processing unit (CPU) coupled to a cache controller, said cache controller coupled to a memory management unit (MMU) and a cache memory, said MMU further coupled to a main memory, an improved method for selectively transferring instruction data stored in said main memory to said cache memory, comprising the steps of: said cache controller transferring N instructions from said main memory to said cache memory by applying virtual addresses corresponding to said N instructions to said MMU, said MMU translating said virtual addresses into real addresses and applying said real addresses to said main memory for retrieval of said N instructions; said cache controller detecting any of said N instructions comprising branch instructions, said branch instructions requiring additional data to be transferred to said cache memory, each of said branch instructions include an address for accessing said additional data in said main memory; said CPU executing said N instructions in parallel with said cache controller detecting said branch instructions such that said cache controller detects a particular branch instruction prior to execution of said particular branch instruction by said CPU; said cache controller determining if said additional data is currently stored in said cache memory, such that if said additional data is not stored in said cache memory, said cache controller transferring said additional data corresponding to said branch instructions to said cache memory from said main memory prior to said CPU executing said branch instruction, said cache controller transferring said additional data by applying said addresses for accessing said main memory to said MMU, said MMU translating said virtual addresses into real addresses and applying said real addresses to said main memory, such that if said MMU is unable to translate the virtual addresses of said additional data, said additional data is not obtained from said main memory until said CPU executes said corresponding branch instruction in said N instructions.