Program counter and indirect address calculation system which concurrently performs updating of a program counter and generation of an effective address

Claim 2

A processor including an instruction decoder receiving an instruction of a variable word length for generating a decoded instruction, and a program counter for indicating an instruction address to be read, said processor allowing a program to be located at any desired location within an address space and also allowing addressing a program with a relative reference to a value of said program counter, said processor comprising: first means for receiving said decoded instruction from said instruction decoder and for summing respective lengths of decoded portions of said instruction of variable word length as instruction decoding proceeds, said first means outputting a total length of said decoded portions of said instruction of variable word length; second means for receiving said total length outputted from said first means and for adding said total length of said decoded portions to a value of said program counter to update said program counter; third means for receiving said value of said program counter to execute an effective address calculation, using said value of said program counter as it existed before said updating of said program counter, for a next instruction; and fourth means, coupled to receive decoded information from said instruction decoder and also coupled to said second means and to said third means, for independently controlling said second means and said third means.

Claim 3

A processor comprising: a program counter coupled to a first bus through which an instruction is supplied and a second bus through which an effective address is supplied, said program counter associated with a first adder for updating a content of said program counter; a register file coupled to said first bus and to said second bus for operatively latching a displacement on said first bus and a value of said program counter supplied on said second bus; an effective address calculation adder coupled to said register file to produce a sum of said displacement and said value of said program counter as a calculated effective address; an effective address latch coupled to said effective address calculation adder for outputting a calculated effective address to said second bus; an instruction decoder coupled to said first bus for generating decoded data; an instruction request controller coupled to receive said decoded data; an instruction request total byte number generator, coupled to receive said decoded data, to generated total byte number information; a program counter update controller controlled by said instruction request controller to control updating of said program counter; a program counter offset supplying means, coupled to said instruction request total byte number generator and to said program counter update controller, to supply an offset value to said first adder associated with said program counter; an effective address generation controller, coupled to receive said decoded data, for controlling said register file and said effective address calculation adder; and a sequencer for enabling said program counter update controller and said effective address generation controller simultaneously such that updating of said program counter and generation of said effective address are concurrently executed.

Claim 4

A processor comprising: a program counter coupled to a first bus through which an instruction is supplied and a second bus through which an effective address is supplied, said program counter associated with a first adder for updating a content of said program counter; a register file coupled to said first bus and to said second bus for operatively latching a displacement on said first bus and a value of said program counter supplied on said second bus; an effective address calculation adder coupled to said register file to produce a sum of said displacement and said value of said program counter as a calculated effective address; an effective address latch coupled to said effective address calculation adder for outputting a calculated effective address to said second bus; an instruction decoder coupled to said first bus for generating decoded data; an instruction request controller coupled to receive said decoded data; an instruction request total byte number generator, coupled to receive said decoded data, to generated total byte number information; a program counter update controller controlled by said instruction request controller to control updating of said program counter; a program counter offset supplying means, coupled to said instruction request total byte number generator and to said program counter update controller, to supply an offset value to said first adder associated with said program counter; an effective address generation controller, coupled to receive said decoded data, for controlling said register file and said effective address calculation adder; and a sequencer for enabling said program counter update controller and said effective address generation controller simultaneously such that updating of said program counter and generation of said effective address are concurrently executed.

Claim 5

A processor for processing an instruction of a variable word length, said processor including an instruction decoder receiving said instruction of variable word length for generating a decoded instruction, and a program counter controlled to indicate a beginning of an instruction to be decoded by a value of said program counter, said processor allowing a program to be located at any desired location within an address space and also allowing addressing a program with a relative reference to said value of said program counter, said processor comprising: first means for receiving said decoded instruction from said instruction decoder and for summing respective lengths of decoded portions of said instruction of variable word length as instruction decoding proceeds, said first means outputting a total length of said decoded portions of said instruction of variable word length; second means, coupled to said program counter, for receiving said total length outputted from said first means and for supplying and adding said total length of said decoded portions to a value of said program counter so as to update said program counter after a decoding of said instruction of variable word length; third means for receiving said value of said program counter as it exists prior to said updating by said second means and a relative address information portion of said decoded instruction and for generating a sum of said value of said program counter as it exists prior to said updating by said second means and said relative address information portion as a program counter relative operand effective address in the course of said decoding of said instruction of variable word length; and a control unit for enabling said second means and said third means simultaneously so that updating of said program counter and generation of said effective address based on an original value of said program counter are concurrently executed.

Claim 6

A processor for processing an instruction of a variable word length, said processor including an instruction decoder receiving said instruction of variable word length for generating a decoded instruction, and a program counter controlled to indicate a beginning of an instruction to be decoded by a value of said program counter, said processor allowing a program to be located at any desired location within an address space and also allowing addressing a program with a relative reference to said value of said program counter, said processor comprising: first means for receiving said decoded instruction from said instruction decoder and for summing respective lengths of decoded portions of said instruction of variable word length as instruction decoding proceeds, said first means outputting a total length of said decoded portions of said instruction of variable word length; second means, coupled to said program counter, for receiving said total length outputted from said first means and for supplying and adding said total length of said decoded portions to a value of said program counter so as to update said program counter after a decoding of said instruction of variable word length; third means for receiving said value of said program counter as it exists prior to said updating by said second means and a relative address information portion of said decoded instruction and for generating a sum of said value of said program counter as it exists prior to said updating by said second means and said relative address information portion as a program counter relative operand effective address in the course of said decoding of said instruction of variable word length; and a control unit for enabling said second means and said third means simultaneously so that updating of said program counter and generation of said effective address based on an original value of said program counter are concurrently executed.

Claim 7

A processor claimed in claim 3 wherein said third means is connected to receive said value of said program counter and displacement information included in said decoded instruction and operates to add said displacement information to said value of said program counter for generating said program counter relative operand effective address.

Claim 8

A processor claimed in claim 3 further including an adder coupled to said program counter only for offsetting said program counter so that the number or time of long bit data addition made directly to said program counter can be decreased.