Patent US5225993A successfully refreshed from Google Patents.
US5225993A
Expired / Lapsed
US
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Design rule test apparatus for testing if mask pattern satisfies design rule and operation method therefor
Assignee: Mitsubishi Electric Corp
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Filing: 1991-02-04
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Granted: 1993-07-06
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Expires: 2011-02-04
Abstract
Abstract An improved computer aided design (CAD) apparatus is disclosed for properly determining if a mask pattern for a large-scale integrated circuit (LSI) satisfies a predetermined design rule. This CAD apparatus includes a figure feature file for storing in advance the feature of the configuration of a contact hole region which should not be recognized as a design error. After a conventional design recognizing process has been conducted, a recognition invalidation process is effected by referring to the figure feature file. Accordingly, the detection of a pseudo-error which is not an essential error is reduced, so that the efficiency of a designing operation with this apparatus is improved.
Inventors
- 👤 Mamoru Iwatsuki
- 👤 Masanori Kanehama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:11
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
198 words
A design rule test apparatus for testing if a designed semiconductor integrated circuit satisfies a predetermined design rule, comprising: overlap detection means for detecting the overlap of one contact hole region and an interconnection region; decision means for determining that there are two or more overlapping portions detected by said overlap detection means in said one contact hole region; width comparison means for comparing the width of each portion in said one contact hole region determined by said decision means with a predetermined value in accordance with said design rule; recognition means responsive to the result of the comparison by said width comparison means for recognizing said one contact hole region as a design error; feature storage means for storing in advance the feature of the configuration of a contact hole region which should not be recognized as a design error; feature comparison means for comparing the feature of the configuration of said one contact hole region recognized by said recognition means with the feature stored in said feature storage means; and invalidation means responsive to the result of the comparison by said feature comparison means for invalidating the recognition of the design error by said recognition means.
Claim 2
Dependent Claim
198 words
A design rule test apparatus for testing if a designed semiconductor integrated circuit satisfies a predetermined design rule, comprising: overlap detection means for detecting the overlap of one contact hole region and an interconnection region; decision means for determining that there are two or more overlapping portions detected by said overlap detection means in said one contact hole region; width comparison means for comparing the width of each portion in said one contact hole region determined by said decision means with a predetermined value in accordance with said design rule; recognition means responsive to the result of the comparison by said width comparison means for recognizing said one contact hole region as a design error; feature storage means for storing in advance the feature of the configuration of a contact hole region which should not be recognized as a design error; feature comparison means for comparing the feature of the configuration of said one contact hole region recognized by said recognition means with the feature stored in said feature storage means; and invalidation means responsive to the result of the comparison by said feature comparison means for invalidating the recognition of the design error by said recognition means.
Claim 3
Dependent Claim
88 words
The design rule test apparatus according to claim 1, wherein the feature of the configuration of said one contact hole region is defined by the data of vectors surrounding said contact hole region, said feature storage means stores the data of the vectors surrounding said contact hole region which should not be recognized as the design error, and said feature comparison means compares the data of the vectors surrounding the contact hole region recognized by said recognition means with the vector data stored in said feature storage means.
Claim 4
Dependent Claim
103 words
The design rule test apparatus according to claim 2, wherein the feature of the configuration of said contact hole region is further defined by the number of vertexes of the configuration of said one contact hole region, said feature storage means further stores data of the number of vertexes of said configuration of said contact hole region which should not be recognized as a design error, and said feature comparison means further compares the data of the number of vertexes of the configuration in said one contact hole region recognized by said recognition means with the data stored in said feature storage means.
Claim 5
Dependent Claim
119 words
The design rule test apparatus according to claim 3, wherein said feature comparison means comprises: first coincidence detection means for detecting a coincidence between the data of the vectors surrounding said one contact hole region recognized by said recognition means and the vector data stored in said feature storage means; second coincidence detection means for detecting a coincidence between the data of the number of vertexes of the configuration of said one contact hole region recognized by said recognition means and the data of the number of vertexes stored in said feature storage means, and said invalidation means invalidates the recognition of the design error by said recognition means in response to said first and second coincidence detection means.
Claim 6
Dependent Claim
39 words
The design rule test apparatus according to claim 1, wherein said overlap detection means comprises logical product means for performing a logical product operation with regard to a figure of said one contact hole region and said interconnection region.
Claim 7
Dependent Claim
31 words
The design rule test apparatus according to claim 1, wherein said design rule test apparatus comprises a computer aided design apparatus for designing a mask pattern of a semiconductor integrated circuit.
Claim 8
Dependent Claim
187 words
An operating method of a design rule test apparatus for testing if a designed semiconductor integrated circuit satisfies a predetermined design rule, said apparatus comprising feature storage means for storing in advance the feature of the configuration of a contact hole region which should not be recognized as a design error, said operating method includes the steps of: detecting the overlap of one contact hole region and an interconnection region; determining that there are two or more overlapping portions in said one contact hole region detected in said overlap detecting step; comparing the width of each portion in said one contact hole region determined in said determining step with a predetermined value in accordance with said design rule; recognizing said one contact hole region as the design error in response to the result of the comparison in said width comparing step; comparing the feature of the configuration of said one contact hole region recognized in said recognizing step with the feature stored in said feature storage means; invalidating the recognition of said design error in response to the result of the comparison in said feature comparing step.
Claim 9
Dependent Claim
187 words
An operating method of a design rule test apparatus for testing if a designed semiconductor integrated circuit satisfies a predetermined design rule, said apparatus comprising feature storage means for storing in advance the feature of the configuration of a contact hole region which should not be recognized as a design error, said operating method includes the steps of: detecting the overlap of one contact hole region and an interconnection region; determining that there are two or more overlapping portions in said one contact hole region detected in said overlap detecting step; comparing the width of each portion in said one contact hole region determined in said determining step with a predetermined value in accordance with said design rule; recognizing said one contact hole region as the design error in response to the result of the comparison in said width comparing step; comparing the feature of the configuration of said one contact hole region recognized in said recognizing step with the feature stored in said feature storage means; invalidating the recognition of said design error in response to the result of the comparison in said feature comparing step.
Claim 10
Dependent Claim
94 words
The operating method according to claim 7, wherein the feature of the configuration of said one contact hole region is defined by data of vectors surrounding said one contact hole region, said feature storage means stores the data of the vectors surrounding said contact hole region which should not be recognized as the design error, and said step of comparing said two features includes the step of comparing the data of the vectors surrounding said one contact hole region recognized in said recognizing step with the vector data stored in said feature storage means.
Claim 11
Dependent Claim
109 words
The operating method according to claim 8, wherein the feature of the configuration of said one contact hole region is further defined by the number of vertexes of the configuration of said one contact hole region, said feature storage means further stores data of the number of vertexes of said configuration of said contact hole region which should not be recognized as the design error, and said step of comparing said two features further includes the step of comparing the data of the number of vertexes of the configuration of said one contact hole region recognized in said recognizing step with the data stored in said feature storage means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |