Patent US5224104A successfully refreshed from Google Patents.
US5224104A
Expired / Lapsed
US
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Real-time address switching circuit
Assignee: Yokogawa Electric Corp
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Filing: 1990-12-21
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Granted: 1993-06-29
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Expires: 2010-12-21
Abstract
Abstract A real-time address switching circuit is adapted for effecting a DRAM multiple-bits parallel test. The real-time address switching circuit includes selectors for effecting the pattern selection for the AX AY addresses to be added to a device under test, a gate for controlling the selectors at the real time, a register for latching the data bit size data and a multiplexer for receiving the outputs of the selectors and switching the AX AY addresses.
Inventors
- 👤 Yoshikuni Iyaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
354 words
A real-time address switching circuit comprises: means for outputting size data, a real-time control signal, an AX address which includes a plurality of first address signals, an AY address which includes a plurality of second address signals, and a multiplexer control signal; a device under test which has a plurality of inputs; a register which latches said size data and has an output; a gate having an output and having two inputs to which are respectively applied said output of said register and said real-time control signal; a first selector having a plurality of outputs, having a plurality of inputs coupled to respective said first address signals, and having means responsive to said output of said gate for selectively supplying to said outputs of said first selector one of a plurality of first signal patterns, each said first signal pattern being a unique combination of signals which are each supplied to a respective said output of said first selector and which are each one of a predetermined logic level and a respective said first address signal; a second selector having a plurality of outputs, having a plurality of inputs coupled to respective said second address signals, and having means responsive to said output of said gate for selectively supplying to said outputs of said second selector one of a plurality of second signal patterns, each said second signal pattern being a unique combination of signals which are each supplied to a respective said output of said second selector and which are each one of a predetermined logic level and a respective said second address signal; and a multiplexer having a first group of inputs each coupled to a respective one of said outputs of said first selector, having a second group of inputs each coupled to a respective one of said outputs of said second selector, having a plurality of outputs each coupled to a respective said input of said device under test, and having-means responsive to said multiplexer control signal for selectively supplying to said outputs of said multiplexer the signals from a responsive one of said first said second groups of inputs.
Claim 2
Dependent Claim
354 words
A real-time address switching circuit comprises: means for outputting size data, a real-time control signal, an AX address which includes a plurality of first address signals, an AY address which includes a plurality of second address signals, and a multiplexer control signal; a device under test which has a plurality of inputs; a register which latches said size data and has an output; a gate having an output and having two inputs to which are respectively applied said output of said register and said real-time control signal; a first selector having a plurality of outputs, having a plurality of inputs coupled to respective said first address signals, and having means responsive to said output of said gate for selectively supplying to said outputs of said first selector one of a plurality of first signal patterns, each said first signal pattern being a unique combination of signals which are each supplied to a respective said output of said first selector and which are each one of a predetermined logic level and a respective said first address signal; a second selector having a plurality of outputs, having a plurality of inputs coupled to respective said second address signals, and having means responsive to said output of said gate for selectively supplying to said outputs of said second selector one of a plurality of second signal patterns, each said second signal pattern being a unique combination of signals which are each supplied to a respective said output of said second selector and which are each one of a predetermined logic level and a respective said second address signal; and a multiplexer having a first group of inputs each coupled to a respective one of said outputs of said first selector, having a second group of inputs each coupled to a respective one of said outputs of said second selector, having a plurality of outputs each coupled to a respective said input of said device under test, and having-means responsive to said multiplexer control signal for selectively supplying to said outputs of said multiplexer the signals from a responsive one of said first said second groups of inputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-28 | 1996-12-28 | 1997-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-28 | 2000-12-28 | 2001-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-28 | 2004-12-28 | 2005-06-29 | $7700.00 | Window Closed / Lapsed |