US5223931A
Expired / Lapsed
US
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Synchronized scanning at horizontal frequency
Assignee: Technicolor USA Inc
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Filing: 1992-09-02
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Granted: 1993-06-29
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Expires: 2012-09-02
Abstract
Abstract A first phase locked loop generates a first timing signal at a first horizontal synchronizing frequency corresponding to a horizontal synchronizing component in a video signal. A converter circuit derives from the first timing signal a second timing signal, having a second frequency at a multiple of the first frequency and subject to a variation in frequency at a rate corresponding to the first frequency. A second phase locked loop comprises a comparator, a low pass filter, a controllable oscillator and a horizontal output deflection stage receives the second timing signal, which can be asymmetric within the period of the first timing signal, and a feedback signal in accordance with the second frequency. The controllable oscillator generates a horizontal synchronizing signal at the second frequency. The second phase locked loop has a characteristic loop response, determined by the low pass filter, preventing the controllable oscillator from changing frequency as fast as the rate of variation of the second timing signal. This drives the error signal for the controllable oscillator toward an average value, resulting in a corrected, symmetric synchronizing signal at the second frequency. The horizontal output deflection stage is synchronized for horizontal scanning in accordance with the second frequency. No additional signal processing circuitry is needed to correct the symmetry of the first timing signal generated by the first phase locked loop or the symmetry of the second timing signal derived by the converter.
Inventors
- 👤 Ronald E. Fernsler
- 👤 Enrique Rodriguez-Cavazos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:14
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/30
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
188 words
A synchronizing system, comprising: a first phase locked loop having a first controllable oscillator and a first comparator, for generating a first timing signal at a first synchronizing frequency corresponding to a synchronizing component in a video signal; means for deriving from said first timing signal and from said first oscillator a second timing signal, having a second frequency at a multiple of said first frequency and being subject to a variation in frequency at a rate corresponding to said first frequency; a second phase locked loop, having a second comparator for receiving said second timing signal and a feedback signal in accordance with said second frequency and a second controllable oscillator for generating a synchronizing signal at said second frequency; and, an output deflection stage, coupled for receiving said synchronizing signal at said second frequency and for generating a retrace signal to which said feedback signal is related, for synchronized scanning in accordance with said second frequency, said second phase locked loop having a characteristic loop response preventing said second controlled oscillator from changing frequency as fast as said rate of variation of said second timing signal.
Claim 2
Dependent Claim
188 words
A synchronizing system, comprising: a first phase locked loop having a first controllable oscillator and a first comparator, for generating a first timing signal at a first synchronizing frequency corresponding to a synchronizing component in a video signal; means for deriving from said first timing signal and from said first oscillator a second timing signal, having a second frequency at a multiple of said first frequency and being subject to a variation in frequency at a rate corresponding to said first frequency; a second phase locked loop, having a second comparator for receiving said second timing signal and a feedback signal in accordance with said second frequency and a second controllable oscillator for generating a synchronizing signal at said second frequency; and, an output deflection stage, coupled for receiving said synchronizing signal at said second frequency and for generating a retrace signal to which said feedback signal is related, for synchronized scanning in accordance with said second frequency, said second phase locked loop having a characteristic loop response preventing said second controlled oscillator from changing frequency as fast as said rate of variation of said second timing signal.
Claim 3
Dependent Claim
25 words
The system of claim 1, wherein said first phase locked loop comprises a feedback path for a feedback signal related to said first timing signal.
Claim 4
Dependent Claim
24 words
The system of claim 1, wherein said means for deriving said second timing signal is coupled between said first and second phase locked loops.
Claim 5
Dependent Claim
34 words
The system of claim 1, wherein said second phase locked loop comprises a low pass filter for controlling said voltage controlled oscillator, said low pass filter having a frequency characteristic defining said loop response.
Claim 6
Dependent Claim
26 words
The system of claim 1, wherein said feedback signal of said second phase locked loop is derived from said retrace pulses from said output deflection stage.
Claim 7
Dependent Claim
33 words
The system of claim 1, wherein said first timing signal has a frequency corresponding to a horizontal synchronizing component in said video signal and said feedback signal is related to horizontal retrace pulses.
Claim 8
Dependent Claim
28 words
The system of claim 1, wherein a sum of successive pulse periods of said second timing signal in each pulse period of said first timing signal is constant.
Claim 9
Dependent Claim
129 words
A synchronizing system, comprising: a first phase locked loop including an oscillator and generating an f H timing signal synchronously with an f H synchronizing component in a video signal: a second phase locked loop, having a comparator for receiving a 2f H timing signal and a 2f H feedback signal, a second oscillator for generating a 2f H horizontal synchronizing signal and an output deflection stage for 2f H synchronized scanning, coupled to said second oscillator and coupled to said comparator; and means coupled between said first and second phase locked loops, responsive to said F H timing signal and said first oscillator from said first phase locked loop for generating said 2f H timing signal as an input to said comparator of said second phase locked loop.
Claim 10
Dependent Claim
129 words
A synchronizing system, comprising: a first phase locked loop including an oscillator and generating an f H timing signal synchronously with an f H synchronizing component in a video signal: a second phase locked loop, having a comparator for receiving a 2f H timing signal and a 2f H feedback signal, a second oscillator for generating a 2f H horizontal synchronizing signal and an output deflection stage for 2f H synchronized scanning, coupled to said second oscillator and coupled to said comparator; and means coupled between said first and second phase locked loops, responsive to said F H timing signal and said first oscillator from said first phase locked loop for generating said 2f H timing signal as an input to said comparator of said second phase locked loop.
Claim 11
Dependent Claim
55 words
The system of claim 8, wherein said 2f H timing signal is subject of a periodic variation in frequency at said f H rate and said second phase locked loop has a characteristic loop response preventing said second oscillator from changing frequency as fast as said rate of variation of said f H timing signal.
Claim 12
Dependent Claim
20 words
The system of claim 9, wherein said means coupled between said first and second phase locked loops comprises digital circuitry.
Claim 13
Dependent Claim
33 words
The system of claim 9, wherein said second phase locked loop comprises a low pass filter for controlling said second oscillator, said low pass filter having a frequency characteristic defining said loop response.
Claim 14
Dependent Claim
19 words
The system of claim 8, wherein said feedback signal is derived from retrace pulse from said output deflection stage.
Claim 15
Dependent Claim
17 words
The system of claim 8, wherein said 2f H feedback signal is related to horizontal retrace pulses.
Claim 16
Dependent Claim
30 words
The system of claim 8, wherein a sum of successive pulse periods of said 2f H timing signal in each pulse period of said f H timing signal is constant.
Claim 17
Dependent Claim
129 words
A synchronizing and deflection system, comprising: a first phase locked loop having an nf H oscillator and a 1/n divider for generating a first timing signal at f H and related to a horizontal synchronizing component in a video signal; counting means preset by said first timing signal and responsive to said nf H oscillator for deriving a second timing signal at mf H ; a horizontal output deflection stage; and, a second phase locked loop having a comparator for receiving said second timing signal and a feedback signal derived from said horizontal output deflection stage and a second oscillator for generating a scan synchronizing signal at mf H , said horizontal output deflection stage being coupled to said second oscillator for synchronized horizontal scanning at mf H .
Claim 18
Dependent Claim
129 words
A synchronizing and deflection system, comprising: a first phase locked loop having an nf H oscillator and a 1/n divider for generating a first timing signal at f H and related to a horizontal synchronizing component in a video signal; counting means preset by said first timing signal and responsive to said nf H oscillator for deriving a second timing signal at mf H ; a horizontal output deflection stage; and, a second phase locked loop having a comparator for receiving said second timing signal and a feedback signal derived from said horizontal output deflection stage and a second oscillator for generating a scan synchronizing signal at mf H , said horizontal output deflection stage being coupled to said second oscillator for synchronized horizontal scanning at mf H .
Claim 19
Dependent Claim
19 words
The system of claim 15, wherein n and m are even valued integers and n is greater than m.
Claim 20
Dependent Claim
13 words
The system of claim 15, wherein n is 32 and m is 2.
Claim 21
Dependent Claim
46 words
The system of claim 15, wherein said second phase locked loop comprises a low pass filter for generating a control signal for said second oscillator which prevents said second oscillator from changing frequency as fast as changes occur in the frequency of said second timing signal.
Claim 22
Dependent Claim
20 words
The system of claim 15, wherein said feedback signal is related to retrace pulses of said horizontal output deflection stage.
Claim 23
Dependent Claim
28 words
The system of claim 15, wherein a sum of successive pulse periods of said second timing signal in each pulse period of said first timing signal is constant.
Claim 24
Dependent Claim
142 words
A synchronizing system, comprising: a source of a video horizontal synchronizing component at a first frequency; means coupled to said source for generating a timing signal synchronized with said horizontal synchronizing component and at a second frequency greater than said first frequency, said timing signal being subject to a timing error due to a periodic perturbation of said timing signal at said first frequency; a horizontal deflection stage; and, a phase locked loop for generating a scan synchronizing signal at said second frequency for synchronized horizontal scanning by said horizontal deflection stage, having means for comparing said timing signal and a feedback signal related to operation of said horizontal deflection stage, said phase locked loop having a characteristic response which substantially averages out said timing error in said timing to substantially preclude introduction of said periodic perturbation into said scan synchronizing signal.
Claim 25
Dependent Claim
142 words
A synchronizing system, comprising: a source of a video horizontal synchronizing component at a first frequency; means coupled to said source for generating a timing signal synchronized with said horizontal synchronizing component and at a second frequency greater than said first frequency, said timing signal being subject to a timing error due to a periodic perturbation of said timing signal at said first frequency; a horizontal deflection stage; and, a phase locked loop for generating a scan synchronizing signal at said second frequency for synchronized horizontal scanning by said horizontal deflection stage, having means for comparing said timing signal and a feedback signal related to operation of said horizontal deflection stage, said phase locked loop having a characteristic response which substantially averages out said timing error in said timing to substantially preclude introduction of said periodic perturbation into said scan synchronizing signal.
Claim 26
Dependent Claim
16 words
The system of claim 21, wherein said second frequency is a multiple of said first frequency.
Claim 27
Dependent Claim
17 words
The system of claim 21, wherein said second frequency is an even multiple of said first frequency.
Claim 28
Dependent Claim
30 words
The system of claim 21, wherein said phase locked loop comprises a controllable oscillator and low pass filter for controlling said oscillator, said low pass filter defining said characteristic response.
Claim 29
Dependent Claim
14 words
The system of claim 21, wherein said feedback signal is related to retrace pulses.
Claim 30
Dependent Claim
36 words
The system of claim 21, wherein said means for generating said timing signal comprises: a second phase locked loop synchronized with said horizontal synchronizing component; and, a frequency converter synchronized with said second phase locked loop.
Claim 31
Dependent Claim
26 words
The system of claim 21, wherein a sum of successive pulse periods of said timing in each pulse period of said synchronizing component is substantially constant.
Claim 32
Dependent Claim
24 words
The system of claim 26, wherein said frequency converter comprises a presettable counter for dividing an oscillator signal from said second phase locked loop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-28 | 1996-12-28 | 1997-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-28 | 2000-12-28 | 2001-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-28 | 2004-12-28 | 2005-06-29 | $7700.00 | Window Closed / Lapsed |