Television receiver

Claim 2

A television receiver including a digital circuit processing an input video signal in a digital mode, means for scanning an electron beam at a frequency which is n times (n being an integer) as high as that of a horizontal synchronizing signal of said video signal, and a clock generating circuit applying a system clock signal to said digital circuit, said clock generating circuit comprising: a phase comparator having a first input to which said horizontal synchronizing signal is applied; a low-pass filter connected to said phase comparator; a voltage controlled oscillator connected to said low-pass filter to generate the system clock signal having a frequency of (n×m×f H ) which is (n×m) times (m being an integer) as high as the frequency (f H ) of said horizontal synchronizing signal; a 1/m frequency divider dividing the frequency of said system clock signal generated from said voltage controlled oscillator by the factor of m. to generate a horizontal deflection drive pulse signal having a frequency of (n×f H ); and a 1/n frequency divider connected to a second input of said phase comparator, said phase comparator, said low-pass filter, said voltage controlled oscillator, said 1/m frequency divider and said 1/n frequency divider constituting a single PLL circuit, and both of said system clock signal and said horizontal deflection drive pulse signal being generated from said PLL circuit.

Claim 3

A television receiver including a digital circuit processing an input video signal in a digital mode, means for scanning an electron beam at a frequency which is n times (n=1, 2, . . . ) as high as that of a horizontal synchronizing signal of said video signal, and a clock generating circuit applying a system clock signal to said digital circuit, said clock generating circuit comprising: a phase comparator having a first input to which said horizontal synchronizing signal of said video signal is applied; a low-pass filter connected to said phase comparator; a voltage controlled oscillator connected to said low-pass filter to generate the system clock signal having a frequency of (n×m×f H ) which is (n×m) times (n, m=1, 2, . . . ) as high as the frequency (f H ) of said horizontal synchronizing signal; a 1/m frequency divider dividing the frequency of said system clock signal generated from said voltage controlled oscillator by the factor of m; and a 1/n frequency divider connected to a second input of said phase comparator, the output signal generated at the frequency of (n×f H ) from said 1/m frequency divider being applied to a horizontal output circuit of a horizontal deflection circuit as a horizontal deflection drive pulse signal, a flyback pulse signal generated from a flyback transformer of said horizontal deflection circuit being applied to said 1/n frequency divider to appear as an output signal having a frequency divided by the factor of n, and the phase of said output signal of said 1/n frequency divider being compared in said phase comparator with that of said horizontal synchronizing signal, said phase comparator, said low-pass filter, said voltage controlled oscillator, said 1/m frequency divider and said 1/n frequency divider constituting a single PLL circuit, and both of said system clock signal and said horizontal deflection drive pulse signal being generated from said PLL circuit.

Claim 4

A television receiver including a digital circuit processing an input video signal in a digital mode, means for scanning an electron beam at a frequency which is n times (n=1, 2, . . . ) as high as that of a horizontal synchronizing signal of said video signal, and a clock generating circuit applying a system clock signal to said digital circuit, said clock generating circuit comprising: a phase comparator having a first input to which said horizontal synchronizing signal of said video signal is applied; a low-pass filter connected to said phase comparator; a voltage controlled oscillator connected to said low-pass filter to generate the system clock signal having a frequency of (n×m×f H ) which is (n×m) times (n, m=1, 2, . . . ) as high as the frequency (f H ) of said horizontal synchronizing signal; a 1/m frequency divider dividing the frequency of said system clock signal generated from said voltage controlled oscillator by the factor of m; and a 1/n frequency divider connected to a second input of said phase comparator, the output signal generated at the frequency of (n×f H ) from said 1/m frequency divider being applied to a horizontal output circuit of a horizontal deflection circuit as a horizontal deflection drive pulse signal, a flyback pulse signal generated from a flyback transformer of said horizontal deflection circuit being applied to said 1/n frequency divider to appear as an output signal having a frequency divided by the factor of n, and the phase of said output signal of said 1/n frequency divider being compared in said phase comparator with that of said horizontal synchronizing signal, said phase comparator, said low-pass filter, said voltage controlled oscillator, said 1/m frequency divider and said 1/n frequency divider constituting a single PLL circuit, and both of said system clock signal and said horizontal deflection drive pulse signal being generated from said PLL circuit.

Claim 5

A television receiver including a digital circuit processing in a digital mode an input video signal including a horizontal synchronizing signal having a predetermined frequency (f H ), a clock generating circuit applying a system clock signal to said digital circuit, and a horizontal deflection circuit to which a horizontal deflection drive pulse signal having a frequency of (n×f H ) which is n times (n being an integer) as high as that of said horizontal synchronizing signal is applied from said clock generating circuit, said clock generating circuit comprising: a phase comparator having a first input to which said horizontal synchronizing signal is applied; a low-pass filter connected to said phase comparator; a voltage controlled oscillator connected to said low-pass filter to generate the system clock signal having a frequency of (n×m×f H ) which is (n×m) times (m being an integer) as high as that of said horizontal synchronizing signal; a 1/m frequency divider dividing the frequency of said system clock signal generated from said voltage controlled oscillator by the factor of m to generate the horizontal deflection drive pulse signal having the frequency of (n×f H ); and a 1/n frequency divider connected to a second input of said phase comparator; said horizontal deflection circuit comprising: a horizontal output circuit to which said horizontal deflection drive pulse signal is applied from said 1/m frequency divider; and a flyback transformer generating a flyback pulse signal in response to a horizontal output signal applied from said horizontal output circuit, said 1/n frequency divider dividing the frequency (n×f H ) of said flyback pulse signal by the factor of n, and said phase comparator comparing the phase of the output signal generated at the frequency of f H from said 1/n frequency divider with that of said horizontal synchronizing signal, said phase comparator, said low-pass filter, said voltage controlled oscillator, said 1/m frequency divider and said 1/n frequency divider constituting a single PLL circuit, and both of said system clock signal and said horizontal deflection drive pulse signal being generated from said PLL circuit.

Claim 6

A television receiver including a digital circuit processing in a digital mode an input video signal including a horizontal synchronizing signal having a predetermined frequency (f H ), a clock generating circuit applying a system clock signal to said digital circuit, and a horizontal deflection circuit to which a horizontal deflection drive pulse signal having a frequency of (n×f H ) which is n times (n being an integer) as high as that of said horizontal synchronizing signal is applied from said clock generating circuit, said clock generating circuit comprising: a phase comparator having a first input to which said horizontal synchronizing signal is applied; a low-pass filter connected to said phase comparator; a voltage controlled oscillator connected to said low-pass filter to generate the system clock signal having a frequency of (n×m×f H ) which is (n×m) times (m being an integer) as high as that of said horizontal synchronizing signal; a 1/m frequency divider dividing the frequency of said system clock signal generated from said voltage controlled oscillator by the factor of m to generate the horizontal deflection drive pulse signal having the frequency of (n×f H ); and a 1/n frequency divider connected to a second input of said phase comparator; said horizontal deflection circuit comprising: a horizontal output circuit to which said horizontal deflection drive pulse signal is applied from said 1/m frequency divider; and a flyback transformer generating a flyback pulse signal in response to a horizontal output signal applied from said horizontal output circuit, said 1/n frequency divider dividing the frequency (n×f H ) of said flyback pulse signal by the factor of n, and said phase comparator comparing the phase of the output signal generated at the frequency of f H from said 1/n frequency divider with that of said horizontal synchronizing signal, said phase comparator, said low-pass filter, said voltage controlled oscillator, said 1/m frequency divider and said 1/n frequency divider constituting a single PLL circuit, and both of said system clock signal and said horizontal deflection drive pulse signal being generated from said PLL circuit.