Resistive fuse circuits for image segmentation and smoothing

Claim 2

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel depletion-mode MOS field effect transistor, and a first and a second p-channel depletion-mode MOS field effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, an electrical connection between the first terminal of the first n-channel transistor and the gate of the first p-channel transistor, an electrical connection between the second terminal of the second n-channel transistor and the gate of the second p-channel transistor, an electrical connection between the gate of the first n-channel transistor, the gate of the second n-channel transistor, the second terminal of the first p-channel transistor, and the first terminal of the second p-channel transistor, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 3

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel junction field-effect transistor, and a first and a second p-channel junction field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, an electrical connection between the first terminal of the first n-channel transistor and the gate of the first p-channel transistor, an electrical connection between the second terminal of the second n-channel transistor and the gate of the second p-channel transistor, an electrical connection between the gate of the first n-channel transistor, the gate of the second n-channel transistor, the second terminal of the first p-channel transistor, and the first terminal of the second p-channel transistor, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 4

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel junction field-effect transistor, and a first and a second p-channel junction field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, an electrical connection between the first terminal of the first n-channel transistor and the gate of the first p-channel transistor, an electrical connection between the second terminal of the second n-channel transistor and the gate of the second p-channel transistor, an electrical connection between the gate of the first n-channel transistor, the gate of the second n-channel transistor, the second terminal of the first p-channel transistor, and the first terminal of the second p-channel transistor, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 5

The resistive fuse circuit element of claims 1 or 2 wherein the first and second n-channel transistors have substantially the same threshold, the first and second p-channel transistors have substantially the same threshold, and the thresholds of the n-channel and p-channel transistors having substantially the same magnitudes but opposite signs.

Claim 6

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, and a first and a second p-channel field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, a first control voltage source electrically connected between the first terminal of the first n-channel transistor and the gate of the first p-channel transistor, a second control voltage source electrically connected between the second terminal of the second n-channel transistor and the gate of the second p-channel transistor, an first electrical connection between the gates of the first and second n-channel transistors, an second electrical connection between the second terminal of the first p-channel transistor and the first terminal of the second p-channel transistor, a third control voltage source electrically connected between said first electrical connection and said second electrical connection, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 7

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, and a first and a second p-channel field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, a first control voltage source electrically connected between the first terminal of the first n-channel transistor and the gate of the first p-channel transistor, a second control voltage source electrically connected between the second terminal of the second n-channel transistor and the gate of the second p-channel transistor, an first electrical connection between the gates of the first and second n-channel transistors, an second electrical connection between the second terminal of the first p-channel transistor and the first terminal of the second p-channel transistor, a third control voltage source electrically connected between said first electrical connection and said second electrical connection, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 8

The resistive fuse circuit element of claim 4 wherein the field-effect transistors are enhancement-mode MOSFETs.

Claim 9

The resistive fuse circuit element of claim 4 wherein the field-effect transistors are JFETs.

Claim 10

The resistive fuse circuit element of claim 4 wherein the first and second n-channel transistors have substantially the same threshold, the first and second p-channel transistors have substantially the same threshold, and the thresholds of the n-channel and p-channel transistors having substantially the same magnitudes but opposite signs.

Claim 11

The resistive fuse circuit element of claim 4 wherein said control voltage sources are generated from field-effect transistors.

Claim 12

The resistive fuse circuit element of claim 4 wherein said control voltages are generated from switched capacitors.

Claim 13

The resistive fuse circuit element of claim 4 wherein said control voltage sources are made variable so that the linear region resistance and the off-voltage of the resistive fuse circuit element can be controlled.

Claim 14

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, and a first and a second p-channel field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, a first control voltage source electrically connected between the first terminal of the resistive fuse and the gate of the first p-channel transistor, a second control voltage source electrically connected between the second terminal of the resistive fuse and the gate of the second p-channel transistor, a third control voltage source electrically connected between the first terminal of the resistive fuse and the gate of the second n-channel transistor, a fourth control voltage source electrically connected between the second terminal of the resistive fuse and the gate of the first n-channel transistor, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, an electrical connection between the second terminal of the first p-channel transistor and the first terminal of the second p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 15

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, and a first and a second p-channel field-effect transistor, each transistor having a gate and a first and second terminal, the first terminal of the resistive fuse being the first terminal of the first n-channel transistor and the second terminal of the resistive fuse being the second terminal of the second n-channel transistor, a first control voltage source electrically connected between the first terminal of the resistive fuse and the gate of the first p-channel transistor, a second control voltage source electrically connected between the second terminal of the resistive fuse and the gate of the second p-channel transistor, a third control voltage source electrically connected between the first terminal of the resistive fuse and the gate of the second n-channel transistor, a fourth control voltage source electrically connected between the second terminal of the resistive fuse and the gate of the first n-channel transistor, an electrical connection between the second terminal of the first n-channel transistor and the first terminal of the first p-channel transistor, an electrical connection between the second terminal of the first p-channel transistor and the first terminal of the second p-channel transistor, and an electrical connection between the second terminal of the second p-channel transistor and the first terminal of the second n-channel transistor.

Claim 16

The resistive fuse circuit element of claim 11 wherein the field-effect transistors are enhancement-mode MOSFETs.

Claim 17

The resistive fuse circuit element of claim 11 wherein the field-effect transistors are JFETs.

Claim 18

The resistive fuse circuit element of claim 11 wherein the first and second n-channel transistors have substantially the same threshold, the first and second p-channel transistors have substantially the same threshold, and the thresholds of the n-channel and p-channel transistors have substantially the same magnitudes but opposite signs.

Claim 19

The resistive fuse circuit element of claim 11 wherein said control voltage sources are generated from field-effect transistors.

Claim 20

The resistive fuse circuit element of claim 11 wherein said control voltages are generated from switched capacitors.

Claim 21

The resistive fuse circuit element of claim 11 wherein said control voltage sources are made variable so that the linear region resistance and the off-voltage of the resistive fuse circuit element can be controlled.

Claim 22

The resistive fuse circuit element of claim 11 wherein said control voltages are generated from a first and a second circuit, said first and third control voltages being generated by said first circuit and said second and fourth control voltages being generated by said second circuit, each said circuit comprising: a first and second constant voltage source, a first and second constant current source, a p-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the source of said p-channel transistor and said first constant current source, an electrical connection between the drain of said p-channel transistor and said second constant voltage source, a n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the gate of said p-channel transistor and the gate of said n-channel transistor, an electrical connection between the drain of said n-channel transistor and said first constant voltage source, and an electrical connection between the source of said n-channel transistor and said second constant current source, whereby said control voltages are provided via: an electrical connection between the gate of said n-channel transistor of said first circuit and the first terminal of the resistive fuse, an electrical connection between the source of said p-channel transistor of said first circuit and the gate of the second n-channel transistor of the resistive fuse, an electrical connection between the source of said n-channel transistor of said first circuit and the gate of the first p-channel transistor of the resistive fuse, an electrical connection between the gate of said n-channel transistor of said second circuit and the second terminal of the resistive fuse, an electrical connection between the source of said p-channel transistor of said second circuit and the gate of the first n-channel transistor of the resistive fuse, and an electrical connection between the source of said n-channel transistor of said second circuit and the gate of the second p-channel transistor of the resistive fuse.

Claim 23

The resistive fuse of claim 11 wherein said control voltages are generated from a first and a second circuit, said first and third control voltages being generated by said first circuit and said second and fourth control voltages being generated by said second circuit, each said circuit comprising: a first and second constant voltage source, a first, second, and third bias voltage source, a first p-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the source of said first p-channel transistor and said first constant voltage source, an electrical connection between the gate of said first p-channel transistor and said first bias voltage source, a first n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the drain of said first p-channel transistor and the drain of said first n-channel transistor, an electrical connection between the gate and the drain of said first n-channel transistor, a second n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the source of said first n-channel transistor and the drain of said second n-channel transistor, an electrical connection between the gate and the drain of said second n-channel transistor, a second p-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the gate of said second n-channel transistor and the source of said second p-channel transistor, an electrical connection between the gate of said second p-channel transistor and the drain of said second p-channel transistor, a third n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the drain of said second p-channel transistor and the drain of said third n-channel transistor, an electrical connection between the gate of said third n-channel transistor and said second bias voltage source, an electrical connection between the source of said third n-channel transistor and said second constant voltage source, a fourth n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the source of said fourth n-channel transistor and said second constant voltage source, an electrical connection between the gate of said fourth n-channel transistor and said third bias voltage source, a fifth n-channel field-effect transistor with a source, a gate, and a drain, an electrical connection between the drain of said fourth n-channel transistor and the source of said fifth n-channel transistor, an electrical connection between the source of said fifth n-channel transistor and the source of said second n-channel transistor, and an electrical connection between the drain of said fifth n-channel transistor and said first constant voltage source, whereby said control voltages are provided via: an electrical connection between the gate of said fifth n-channel transistor of said first circuit and the first terminal of the resistive fuse, an electrical connection between the gate of said first n-channel transistor of said first circuit and the gate of the second n-channel transistor of the resistive fuse, an electrical connection between the gate of said second p-channel transistor of said first circuit and the gate of the first p-channel transistor of the resistive fuse, an electrical connection between the gate of said fifth n-channel transistor of said second circuit and the second terminal of the resistive fuse, an electrical connection between the gate of said first n-channel transistor of said second circuit and the gate of the first n-channel transistor of the resistive fuse, and an electrical connection between the gate of said second p-channel transistor of said second circuit and the gate of the second p-channel transistor of the resistive fuse.

Claim 24

The resistive fuse circuit element of claims 18 or 19 wherein the field-effect transistors are enhancement-mode MOSFETs.

Claim 25

The resistive fuse circuit element of claims 18 or 19 wherein the field-effect transistors are JFETs.

Claim 26

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, each transistor having a gate, source, and drain, the first terminal of the resistive fuse being the gate of the first n-channel transistor and the second terminal of the resistive fuse being the gate of the second n-channel transistor, a first and a second p-channel field-effect transistor, each transistor having a gate, source, and drain, a third and fourth n-channel field-effect transistor, each transistor having a gate, and a first and second terminal, a fifth n-channel field-effect transistor having a gate, a source, and a drain, a first and second constant voltage source, a first and second bias voltage source, an electrical connection between the first constant voltage source and each of the sources of the first and the second p-channel transistors, an electrical connection between the gates of the first and the second p-channel transistors, an electrical connection between the gates of the first and the second p-channel transistors and said first bias voltage source, an electrical connection between the drain of the first p-channel transistor and the drain of the first n-channel transistor, an electrical connection between the drain of the first p-channel transistor and the gate of the third n-channel transistor, an electrical connection between the drain of the second p-channel transistor and the drain of the second n-channel transistor, an electrical connection between the drain of the second p-channel transistor and the gate of the fourth n-channel transistor, an electrical connection between the gate of the first n-channel transistor and the first terminal of the third n-channel transistor, an electrical connection between the second terminal of the third n-channel transistor and the first terminal of the fourth n-channel transistor, an electrical connection between the second terminal of the fourth n-channel transistor and the gate of the second n-channel transistor, an electrical connection between the sources of the first and the second n-channel transistors, an electrical connection between the sources of the first and the second n-channel transistors and the drain of the fifth n-channel transistor, an electrical connection between the gate of the fifth n-channel transistor and said second bias voltage source, and an electrical connection between the source of the fifth n-channel transistor and said second constant voltage source.

Claim 27

A resistive fuse circuit element having a first and second terminal comprising: a first and a second n-channel field-effect transistor, each transistor having a gate, source, and drain, the first terminal of the resistive fuse being the gate of the first n-channel transistor and the second terminal of the resistive fuse being the gate of the second n-channel transistor, a first and a second p-channel field-effect transistor, each transistor having a gate, source, and drain, a third and fourth n-channel field-effect transistor, each transistor having a gate, and a first and second terminal, a fifth n-channel field-effect transistor having a gate, a source, and a drain, a first and second constant voltage source, a first and second bias voltage source, an electrical connection between the first constant voltage source and each of the sources of the first and the second p-channel transistors, an electrical connection between the gates of the first and the second p-channel transistors, an electrical connection between the gates of the first and the second p-channel transistors and said first bias voltage source, an electrical connection between the drain of the first p-channel transistor and the drain of the first n-channel transistor, an electrical connection between the drain of the first p-channel transistor and the gate of the third n-channel transistor, an electrical connection between the drain of the second p-channel transistor and the drain of the second n-channel transistor, an electrical connection between the drain of the second p-channel transistor and the gate of the fourth n-channel transistor, an electrical connection between the gate of the first n-channel transistor and the first terminal of the third n-channel transistor, an electrical connection between the second terminal of the third n-channel transistor and the first terminal of the fourth n-channel transistor, an electrical connection between the second terminal of the fourth n-channel transistor and the gate of the second n-channel transistor, an electrical connection between the sources of the first and the second n-channel transistors, an electrical connection between the sources of the first and the second n-channel transistors and the drain of the fifth n-channel transistor, an electrical connection between the gate of the fifth n-channel transistor and said second bias voltage source, and an electrical connection between the source of the fifth n-channel transistor and said second constant voltage source.

Claim 28

The resistive fuse circuit element of claim 22, in the absence of said electrical connection between the second terminal of the third n-channel transistor and the first terminal of the fourth n-channel transistor, further comprising: a third p-channel field-effect transistor having a gate, a source, and a drain, a sixth n-channel field-effect transistor having a gate, and a first and second terminal, a seventh and eighth n-channel field-effect transistor each transistor having a gate, a source, and a drain, a third bias voltage source, an electrical connection between the second terminal of the third n-channel transistor and the first terminal of the sixth n-channel transistor, an electrical connection between the second terminal of the sixth n-channel transistor and the first terminal of the fourth n-channel transistor, an electrical connection between the gate of the sixth n-channel transistor and the gate of the seventh n-channel transistor, an electrical connection between the gate and the drain of the seventh n-channel transistor, an electrical connection between the drain of the seventh n-channel transistor and the drain of the third p-channel transistor, an electrical connection between the gate of the third p-channel transistor and said third bias voltage source, an electrical connection between the source of the third p-channel transistor and said first constant voltage source, an electrical connection between the source of the seventh n-channel transistor and the drain of the eighth n-channel transistor, an electrical connection between the drain and the gate of the eighth n-channel transistor, and an electrical connection between the source of the eighth n-channel transistor and the drain of the fifth n-channel transistor.

Claim 29

The resistive fuse circuit element of claims 22 or 23 wherein the field-effect transistors are enhancement-mode MOSFETs.

Claim 30

The resistive fuse circuit element of claims 22 or 23 wherein the field-effect transistors are JFETs.

Claim 31

The resistive fuse circuit element of claims 22 or 23 wherein said first and second n-channel field-effect transistors have substantially the same threshold, said first and second p-channel field-effect transistors have substantially the same threshold, and said third and fourth n-channel field-effect transistors have substantially the same threshold.

Claim 32

The resistive fuse circuit element of any of claims 1, 2, 4, 11, 18, 19, 22, or 23 fabricated with an oxide layer sufficiently thin to reduce back-gate effect.

Claim 33

A microchip comprising a two-dimensional grid of resistive fuse circuit elements of the types of any of claims 1, 2, 4, 11, 18, 19, 22, or 23 wherein each node of said grid is connected to each of its nearest neighbors by a resistive fuse circuit element.

Claim 34

A microchip comprising a two-dimensional grid of resistive fuse circuit elements of the type of claim 11 wherein each node of said grid is connected to each of its nearest neighbors by a resistive fuse circuit element, comprising only one pair of control voltage sources at each node which act as the first and third control voltage sources (or equivalently as the second and fourth control voltage sources) for every resistive fuse circuit element connected at said node.

Claim 35

A microchip comprising a two-dimensional grid of resistive fuse circuit elements of the types of claims 18 or 19, wherein each node of said grid is connected to each of its nearest neighbors by a resistive fuse circuit element, comprising only one said circuit at each node which acts as the first and third control voltage sources (or equivalently as the second and fourth control voltages sources) for every resistive fuse circuit element connected at said node.

Claim 36

A microchip comprising a two-dimensional grid of resistive fuse circuit elements wherein each node of said grid is connected to each of its nearest neighbors by a resistive fuse circuit element of a first or second type, said first type being the element of claim 11 and said second type being either of the elements of claims 18 or 19, comprising only one pair of control voltage sources at each node connected to an element of the first type, said pair acting as the first and third control voltage sources (or equivalently as the second and fourth control voltage sources) for every element of the first type connected at said node, and comprising only one control voltage circuit at each node connected to an element of the second type, said circuit acting as the first and third control voltage sources (or equivalently as the second and fourth control voltages sources) for every element of the second type connected at said node.

Claim 37

The microchip of claim 28 wherein each said node is functionally connected to a sensing device which converts light into an electronic signal, whereby a voltage is generated at each said node which is in relation to the intensity of light incident on each said device.

Claim 38

The microchip of claim 32 wherein said sensing elements are integrated directly in the microchip.

Claim 39

The microchip of claim 32 wherein each said node is electrically connected to ground by a capacitor and the voltage across the capacitor is generated by said sensing device.

Claim 40

The microchip of claim 32 wherein each node is electrically connected to ground by a resistor in series with a voltage generated by said sensing device.