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US5222244A
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Method of modifying a microinstruction with operands specified by an instruction held in an alias register
Assignee: Intel Corp
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Filing: 1990-12-20
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Granted: 1993-06-22
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Expires: 2010-12-20
Abstract
Abstract An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.
Inventors
- 👤 Adrian Carbine
- 👤 Frank S. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:25
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30192; G06F9/22; G06F9/28; G06F9/30145; G06F9/34; G06F9/35
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
158 words
In an instruction sequencer including an alias register set (116), a microcode translation ROM (122) that stores a microcode flow which implements a macroinstruction, and a machine bus (110), said alias register set including a current alias register, said macroinstruction including an assembler mnemonic and an operand, a method comprising the steps of: (A) storing (158; 160) said macroinstruction so that said fields of said macroinstruction are available throughout execution of a microcode flow which implements said macroinstruction; (B) decoding said assembler mnemonic in said current alias register to determine which one field of said fields is to be substituted with a field of said current alias register; (C) reading (164) a microinstruction from said microcode translation ROM (122), said microinstruction including fields; (D) replacing (166) one of said fields of said microinstruction with said operand in said alias register to thereby produce a grafted instruction; and, (E) issuing (168) said grafted instruction on said machine bus (110).
Claim 2
Dependent Claim
158 words
In an instruction sequencer including an alias register set (116), a microcode translation ROM (122) that stores a microcode flow which implements a macroinstruction, and a machine bus (110), said alias register set including a current alias register, said macroinstruction including an assembler mnemonic and an operand, a method comprising the steps of: (A) storing (158; 160) said macroinstruction so that said fields of said macroinstruction are available throughout execution of a microcode flow which implements said macroinstruction; (B) decoding said assembler mnemonic in said current alias register to determine which one field of said fields is to be substituted with a field of said current alias register; (C) reading (164) a microinstruction from said microcode translation ROM (122), said microinstruction including fields; (D) replacing (166) one of said fields of said microinstruction with said operand in said alias register to thereby produce a grafted instruction; and, (E) issuing (168) said grafted instruction on said machine bus (110).
Claim 3
Dependent Claim
100 words
The method in accordance with claim 1 wherein said alias register set includes a first register and a second register, and a translate block bit, said method comprising the further steps of: (F) setting said translate block bit to a first state or to a second state; (G) selecting for storing either said first register in response to said translate block bit being in said first state or said second register in response to said translate block bit being in said second state, resulting in there being one selected register; (H) storing a first microinstruction in said one selected register.
References Cited (Backward Citations)
US5136696A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |