Single-chip microprocessor having variable memory address mapping

Claim 2

A microprocessor provided on a single chip electrically connectable to another memory and external terminals, comprising: a first internal memory; a central processing unit, operatively coupled to said first internal memory, executing instruction; address generating means for generating an address for accessing said first internal memory; reset means for resetting the central processing unit in response to receiving a reset signal; holding means for holding memory address mapping information and for receiving from the external terminals the memory address mapping information in response to receipt of the reset signal; and access control means, operatively coupled to said first internal memory, to said holding means and to said address generating means, for enabling an access to the another memory by assigning an address region to the another memory when disabling an access to said first internal memory based on the memory address mapping information and the address.

Claim 3

The microprocessor as claimed in claim 1, wherein said another memory comprises a memory external to the microprocessor.

Claim 4

The microprocessor as claimed in claim 1, which further comprises a second internal memory corresponding to the another memory.

Claim 5

The microprocessor as claimed in claim 1, wherein said first internal memory includes means for storing the memory address mapping information.

Claim 6

The microprocessor as claimed in claim 1, wherein said first internal memory comprises a read only memory connected to store instructions.

Claim 7

The microprocessor as claimed in claim 1, which further comprises: reset means for initially setting the microprocessor by outputting a control signal in response to receiving the reset signal.

Claim 8

The microprocessor as claimed in claim 6, wherein said first internal memory includes means for storing the memory address mapping information, and said holding means comprises an internal address decoder for holding the memory address mapping information which is read out of said first internal memory when said reset means outputs the control signal.

Claim 9

The microprocessor as claimed in claim 6, wherein said first internal memory includes means for storing the memory address mapping information, and said access control means comprises an internal address decoder for enabling an access to said first internal memory by outputting an enable signal during a time in which a value of at least a portion of the memory address mapping information matches a value of a portion of the address generated by said address generating means.

Claim 10

The microprocessor as claimed in claim 8, wherein said holding means includes means for holding a variable value of the memory address mapping information that depends on a location of the address region which is allocated for said first internal memory.

Claim 11

The microprocessor as claimed in claim 1, wherein said address generating means comprises a program counter for incrementing a count every time in instruction is executed by said central processing unit and for generating the address of an instruction which is to be executed next.

Claim 12

The microprocessor as claimed in claim 1, wherein said first internal memory comprises a read only memory which stores instructions, and said another memory comprises a random access memory.

Claim 13

The microprocessor as claimed in claim 1, wherein said first internal memory includes means for storing the memory address mapping information, and said holding means includes means for holding a variable value of the memory address mapping information that depends on a location of the address region which is allocated for said first internal memory.

Claim 14

A microprocessor provided on a single chip electrically connectable to another memory and external terminals, comprising: a first internal memory; a central processing unit, operatively coupled to said first internal memory, executing instruction; address generating means for generating an address for accessing said first internal memory; holding means for holding memory address mapping information; access control means, operatively coupled to said first internal memory, to said holding means and to said address generating means, for enabling an access to the another memory by assigning an address region to the another memory when disabling an access to said first internal memory based on the memory address mapping information and the address; a data bus coupled to said central processing unit, to said first internal memory, to the external terminals and to said holding means; and an address bus coupled to said central processing unit, to said address generating means, to said first internal memory and to said access control means, said holding means including a flip-flop connected to hold the memory address mapping information which is received via said data bus from the external terminals in response to a reset signal, said access control means including a detection circuit for detecting whether or not the address received via said address bus matches the memory address mapping information held in said flip-flop.

Claim 15

A microprocessor provided on a single chip electrically connectable to another memory and external terminals, comprising: a first internal memory; a central processing unit, operatively coupled to said first internal memory, executing instruction; address generating means for generating an address for accessing said first internal memory; holding means for holding memory address mapping information; access control means, operatively coupled to said first internal memory, to said holding means and to said address generating means, for enabling an access to the another memory by assigning an address region to the another memory when disabling an access to said first internal memory based on the memory address mapping information and the address; a data bus coupled to said central processing unit, to said first internal memory, to the external terminals and to said holding means; and an address bus coupled to said central processing unit, to said address generating means, to said first internal memory and to said access control means, said holding means including a flip-flop connected to hold the memory address mapping information which is received via said data bus from the external terminals in response to a reset signal, said access control means including a detection circuit for detecting whether or not the address received via said address bus matches the memory address mapping information held in said flip-flop.