Patent US5222214A successfully refreshed from Google Patents.
US5222214A
Expired / Lapsed
US
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Image processing using a ram and repeat read-modify-write operation
Assignee: International Business Machines Corp
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Filing: 1990-06-25
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Granted: 1993-06-22
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Expires: 2010-06-25
Abstract
Abstract An image processing system adaptable to pattern recognition that can serve any image width using a minimum of additional hardware by constructing a line buffer using a RAM and filling the RAM with image data while repeating the RMW (Read-Modify-Write) operation. To increase the processing speed, data packing of the line buffer (RAM) is performed on a multiple-bit basis rather than a bit-by-bit basis, that is, the number of bits written into the line buffer by one RMW operation is increased, for example, to 2, 4, or 8, so that the processing speed can be increased accordingly. An appropriate mask processing system is disclosed for processing the data so packed in the line buffer.
Inventors
- 👤 Yoshinao Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:19
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60; G06T5/00; G06T5/20
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
283 words
A system for processing image data in the form of bits arranged in parallel lines and in which lines N bits are arranged in the line direction, comprising: (a) Random Access Memory (RAM) means for storing said image data, having storage locations defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction, and comprising n small buffers provided by logically dividing the bit width of said RAM means into n portions, where n is an integer not smaller than 2 and is a divisor of N; (b) means for sequentially fetching consecutive sets of n bits from a line of image data in the line direction of the image data for storing in said RAM means: (c) means for sequentially selecting each of N/n addresses of the RAM means for successively storing said sequentially fetched consecutive sets of n bits; (d) means for discarding one bit from an end of each set of data bits stored in each of said n small buffers at a selected address and shifting the storage location positions of the remaining data bits of each of said sets of data bits by one bit in the bit width direction of the RAM means to produce a vacant bit position in each of said sets of data bits at the selected address; and (e) means for placing one of the n bits fetched by said fetching means in the vacant bit position in each of said sets of data bits and respectively storing each of said sets of data bits including said fetched bits in the n small buffers in said RAM means at said selected address.
Claim 2
Independent Claim
283 words
A system for processing image data in the form of bits arranged in parallel lines and in which lines N bits are arranged in the line direction, comprising: (a) Random Access Memory (RAM) means for storing said image data, having storage locations defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction, and comprising n small buffers provided by logically dividing the bit width of said RAM means into n portions, where n is an integer not smaller than 2 and is a divisor of N; (b) means for sequentially fetching consecutive sets of n bits from a line of image data in the line direction of the image data for storing in said RAM means: (c) means for sequentially selecting each of N/n addresses of the RAM means for successively storing said sequentially fetched consecutive sets of n bits; (d) means for discarding one bit from an end of each set of data bits stored in each of said n small buffers at a selected address and shifting the storage location positions of the remaining data bits of each of said sets of data bits by one bit in the bit width direction of the RAM means to produce a vacant bit position in each of said sets of data bits at the selected address; and (e) means for placing one of the n bits fetched by said fetching means in the vacant bit position in each of said sets of data bits and respectively storing each of said sets of data bits including said fetched bits in the n small buffers in said RAM means at said selected address.
Claim 3
Dependent Claim
53 words
An image processing system as set forth in claim 1 wherein at least two values are specifiable as the divisors of said RAM means in determining the number of small buffers provided and said means (b) to (e) are provided for the number of small buffers determined by each of said specifiable divisors.
Claim 4
Dependent Claim
129 words
An image processing system as set forth in claim 1 further comprising: (f) means for fetching the image data one bit at a time, (g) means for sequentially selecting N addresses of the RAM means, (h) means for discarding one of the data bits from an end of each set of data bits stored at each selected address and shifting the storage location positions of the remaining data bits of said each set of data bits by one bit in the bit width direction of the RAM means to produce a vacant bit position in said each set of data bits, and (i) means for inserting one bit fetched from said means (f) into the vacant bit positions of said each set of data bits of said selected addresses.
Claim 5
Independent Claim
261 words
A system for processing data in the form of a bit stream representing the lines of an image, comprising: (a) Random Access Memory (RAM) means, having storage bit positions defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction, for storing said image data bits in n small buffers provided by logically dividing the bit width of said RAM means into n portions, where n is an integer not smaller than 2; (b) means for sequentially fetching consecutive sets of n bits of the image data bit stream; (c) means for sequentially selecting, from successive addresses of said RAM means, n equally-spaced bit positions in the bit width direction, with each of said bit positions respectively disposed in each of said n small buffers, and for producing a signal indicative of a selection; (d) means, responsive to a signal indicative of a selection by said selecting means, for discarding the bit at each position selected by said selecting means and shifting the remaining bits in the bit width direction, and for producing a signal indicative of a selection; and (e) means, responsive to a signal indicative of a shifting of said remaining bits, for disposing the n bits fetched by said fetching means consecutively in the respective vacant bit positions and storing said n bits and remaining bits sequentially in respective addresses in said RAM means, after each shifting, whereby each of said small buffers is sequentially filled with bits representing a portion of said lines of image data.
Claim 6
Independent Claim
261 words
A system for processing data in the form of a bit stream representing the lines of an image, comprising: (a) Random Access Memory (RAM) means, having storage bit positions defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction, for storing said image data bits in n small buffers provided by logically dividing the bit width of said RAM means into n portions, where n is an integer not smaller than 2; (b) means for sequentially fetching consecutive sets of n bits of the image data bit stream; (c) means for sequentially selecting, from successive addresses of said RAM means, n equally-spaced bit positions in the bit width direction, with each of said bit positions respectively disposed in each of said n small buffers, and for producing a signal indicative of a selection; (d) means, responsive to a signal indicative of a selection by said selecting means, for discarding the bit at each position selected by said selecting means and shifting the remaining bits in the bit width direction, and for producing a signal indicative of a selection; and (e) means, responsive to a signal indicative of a shifting of said remaining bits, for disposing the n bits fetched by said fetching means consecutively in the respective vacant bit positions and storing said n bits and remaining bits sequentially in respective addresses in said RAM means, after each shifting, whereby each of said small buffers is sequentially filled with bits representing a portion of said lines of image data.
Claim 7
Dependent Claim
95 words
A system as in claim 4 wherein said fetching means (b) comprises latch means for sequentially receiving n bits of the image data bit stream, and said disposing means (e) comprises: means for sequentially reading to said latch means the remaining bits from each address of said RAM means upon each shifting thereof such that the n bits are disposed in said vacant bit positions; and means for sequentially writing the contents of said latch means back into the respective addresses in said RAM means from which the remaining bits in said contents were read.
Claim 8
Dependent Claim
30 words
A system as in claim 5 wherein said means for sequentially reading to said latch means comprises means for reading said bits through an AND gate and an OR gate.
Claim 9
Dependent Claim
31 words
A system as in claim 5 wherein said fetching means (b) further comprises shift register means for sequentially transferring n bits of the image data bit stream to said latch means.
Claim 10
Dependent Claim
31 words
A system as in claim 7 wherein said fetching means (b) further comprises means for transferring said n bits to said latch means through an AND gate and an OR gate.
Claim 11
Dependent Claim
16 words
A system as in claim 5 wherein said fetching means (b) further comprises a barrel shifter.
Claim 12
Dependent Claim
46 words
A system as in claim 9 wherein said disposing means (e) further comprises bit sorter means for receiving the n bits of the image data bit stream from said barrel shifter and mixing said n bits with said remaining bits for storage in said RAM means.
Claim 13
Dependent Claim
103 words
A system as in claim 4 wherein said disposing means (e) comprises: read-in register means for sequentially receiving the contents of the storage bit positions read out from each address of said RAM means; write-in register means for sequentially receiving the contents of said read-in register means, after the discarding and shifting of the bits therein by said discarding and shifting means, and for receiving the n bits fetched by said fetching means in the bit positions vacated in the bit discarding operation; and means for sequentially writing the contents of said write-in register means into the respective addresses of said RAM means.
Claim 14
Dependent Claim
36 words
A system as in claim 4 further comprising mask processing means for processing the bits in said small buffers representing portions of said lines of image data, said processing means comprising a plurality of shift registers.
Claim 15
Dependent Claim
34 words
A system as in claim 12 wherein said plurality of shift registers comprise a set of shift registers, each having means for receiving n bits in parallel and having tail bits for mask processing.
Claim 16
Dependent Claim
36 words
A system as in claim 13 wherein and all but one of said set of shift registers receives sets of n bits representing corresponding portions of successive lines of said image data from said RAM means.
Claim 17
Dependent Claim
45 words
A system as in claim 13 wherein said mask processing means further comprises means for processing said tail bits and producing an output, and circuit means for receiving and processing the output of said tail bit processing means and producing result bits in accordance therewith.
Claim 18
Dependent Claim
57 words
A system as in claim 15 wherein said RAM means produces an output and said fetching means (b) further comprises a barrel shifter which produces an output and said mask processing means further comprises bit aligner means for receiving the outputs of said barrel shifter and said RAM means and producing an output to said circuit means.
Claim 19
Dependent Claim
36 words
A system as in claim 4 wherein n is an even integer, N is the bit width of the lines of said image, and said RAM means comprises a bit width of N and N/n addresses.
Claim 20
Independent Claim
237 words
A method for processing data in the form of a bit stream representing the lines of an image, comprising the steps of: providing a Random Access Memory (RAM) having storage bit positions defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction; storing said image data in n small buffers in said RAM, provided by logically dividing the bit width of said RAM into n portions, where n is an integer not smaller than 2; sequentially fetching consecutive sets of n bits of the image data bit stream; sequentially selecting, from successive addresses of said RAM means, n equally-spaced bit positions in the bit width direction, with each of said bit positions respectively disposed in each of said n small buffers; upon each selection, discarding the bit at each position selected and shifting the storage location positions of the remaining bits by one bit in the bit width direction to produce a vacant bit position in each of said n small buffers; and upon each shifting of said remaining bits, disposing the n bits fetched by said fetching means consecutively in the respective vacant bit positions; and storing said n bits and remaining bits sequentially in respective addresses in said RAM means, after each shifting, whereby each of said small buffers is sequentially filled with bits representing a portion of said lines of image data.
Claim 21
Independent Claim
237 words
A method for processing data in the form of a bit stream representing the lines of an image, comprising the steps of: providing a Random Access Memory (RAM) having storage bit positions defined by a series of bit addresses in one direction and a bit width in a direction normal to said one direction; storing said image data in n small buffers in said RAM, provided by logically dividing the bit width of said RAM into n portions, where n is an integer not smaller than 2; sequentially fetching consecutive sets of n bits of the image data bit stream; sequentially selecting, from successive addresses of said RAM means, n equally-spaced bit positions in the bit width direction, with each of said bit positions respectively disposed in each of said n small buffers; upon each selection, discarding the bit at each position selected and shifting the storage location positions of the remaining bits by one bit in the bit width direction to produce a vacant bit position in each of said n small buffers; and upon each shifting of said remaining bits, disposing the n bits fetched by said fetching means consecutively in the respective vacant bit positions; and storing said n bits and remaining bits sequentially in respective addresses in said RAM means, after each shifting, whereby each of said small buffers is sequentially filled with bits representing a portion of said lines of image data.
Claim 22
Dependent Claim
93 words
A method as in claim 18 further comprising the steps of: providing a latch for sequentially receiving the sequentially fetched consecutive sets of n bits of the image data bit stream; sequentially reading to said latch the remaining bits from each address of said RAM upon each shifting thereof such that said latch contains said remaining bits with the n bits disposed in said vacant bit positions; and sequentially writing the contents of said latch back into the respective addresses in said RAM from which the remaining bits in said contents were read.
Claim 23
Dependent Claim
35 words
A method as in claim 18 wherein n is an even integer, N is the bit width of the lines of said image, and said RAM comprises a bit width of N and N/n addresses.
References Cited (Backward Citations)
US4827249A
Cited
US4779223A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |