Low-cost display controller comprising a DMA or communications controller operating under processor control

Claim 2

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display and supplying the data from the memory means directly to the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals including display synchronization signals to cause the display to display the image represented by the transferred data.

Claim 3

The display arrangement of claim 1 wherein the control signals generated by the generating means of the processor comprise horizontal and vertical sync signals.

Claim 4

The display arrangement of claim 1 wherein the causing means of the programmable processor repeatedly sends a command to the DMA or communications controller, and the DMA or communications controller responds to each command received from the processor by once transferring to the display a predetermined amount of data from the memory means.

Claim 5

The display arrangement of claim 3 wherein the predetermined amount of data represents one line of the image.

Claim 6

The display arrangement of claim 3 wherein the predetermined amount of data represents one frame of the image.

Claim 7

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly sending a command to the DMA or communications controller to cause the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the DMA or communications controller responds to each command received from the processor by once transferring to the display a predetermined amount of data from the memory means, the DMA or communications controller sends an interrupt to the processor following each transfer of the predetermined amount of data, the generating means of the processor responds to receipt of each interrupt by generating a horizontal sync signal, the causing means of the processor responds to receipt of each interrupt by sending the command to the DMA or communications controller, and the generating means of the processor further responds to receipt of each Nth interrupt, where N is a number of lines in a frame of the image, by generating a vertical sync signal.

Claim 8

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly sending a command to the DMA or communications controller to cause the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the DMA or communications controller responds to each command received from the processor by once transferring to the display a predetermined amount of data from the memory means, the DMA or communications controller sends an interrupt to the processor following each transfer of the predetermined amount of data, the generating means of the processor responds to receipt of each interrupt by generating a horizontal sync signal, the causing means of the processor responds to receipt of each interrupt by sending the command to the DMA or communications controller, and the generating means of the processor further responds to receipt of each Nth interrupt, where N is a number of lines in a frame of the image, by generating a vertical sync signal.

Claim 9

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the memory means store data representing a line of the image to be displayed on the display; the DMA or communications controller comprises means for retrieving data from the memory means, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit serial data stream when retrieved data are being transmitted at the first output port, and a third output port for transmitting a signal to a sync input port of the display; the causing means of the programmable processor cause the DMA or communications controller to periodically retrieve from memory and transmit at the first output port data representing a line of the image frame; and the generating means of the programmable processor transmit a signal at the third port following each transmission by the first port of data representing a line of the image.

Claim 10

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the memory means store data representing a line of the image to be displayed on the display; the DMA or communications controller comprises means for retrieving data from the memory means, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit serial data stream when retrieved data are being transmitted at the first output port, and a third output port for transmitting a signal to a sync input port of the display; the causing means of the programmable processor cause the DMA or communications controller to periodically retrieve from memory and transmit at the first output port data representing a line of the image frame; and the generating means of the programmable processor transmit a signal at the third port following each transmission by the first port of data representing a line of the image.

Claim 11

The display arrangement of claim 7 wherein the DMA or communications controller further comprises means for issuing an interrupt to the processor following each transmittal at the first output port of data representing a line of the image; and the causing means of the processor cause the DMA or communications controller to retrieve from memory and transmit at the first output port data representing a next line of the image, in response to receipt of each interrupt.

Claim 12

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the memory means store data representing lines of an image frame to be displayed on the display; the DMA or communications controller comprises means for retrieving data from the memory means, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit serial data stream when retrieved data are being transmitted at the first output port, a third output port for transmitting a signal to a horizontal sync input port of the display, and a fourth output port for transmitting a signal to a vertical sync input port of the display; the causing means of the programmable processor cause the DMA or communications controller to periodically retrieve from memory and transmit at the first port data representing a line of the image frame; and the generating means of the programmable processor transmit a horizontal sync signal at the third port following each transmission by the first port of data representing a line of the image frame, and transmit a vertical sync signal at the fourth port following transmission by the first port of data representing a last line of the image frame.

Claim 13

A display arrangement comprising: memory means for storing data representative of an image to be displayed; a display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data; wherein the memory means store data representing lines of an image frame to be displayed on the display; the DMA or communications controller comprises means for retrieving data from the memory means, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit serial data stream when retrieved data are being transmitted at the first output port, a third output port for transmitting a signal to a horizontal sync input port of the display, and a fourth output port for transmitting a signal to a vertical sync input port of the display; the causing means of the programmable processor cause the DMA or communications controller to periodically retrieve from memory and transmit at the first port data representing a line of the image frame; and the generating means of the programmable processor transmit a horizontal sync signal at the third port following each transmission by the first port of data representing a line of the image frame, and transmit a vertical sync signal at the fourth port following transmission by the first port of data representing a last line of the image frame.

Claim 14

The display arrangement of claim 9 wherein the DMA or communications controller further comprises means for issuing an interrupt to the processor following each transmittal at the first output port of data representing a line of the image frame, and the causing means of the processor cause the DMA or communications controller to retrieve from memory and transmit at the first output port data representing a next line of the image frame, in response to receipt of each interrupt.

Claim 15

A display controller comprising: a DMA or communications controller responsive to each first command received from a processor by once transferring from a memory to a display a predetermined amount of data representing at least one line of an image to be displayed on the display, and for issuing an interrupt following each transfer of the predetermined amount of data; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for sending one first command to the DMA or communications controller and thereafter responsive to receipt of each interrupt for sending a next first command to the DMA or communications controller, and means responsive to receipt of each interrupt for generating a sync signal for the display, to cause the display to display the image represented by the transferred data.

Claim 16

A display controller comprising: a DMA or communications controller responsive to each first command received from a processor by once transferring from a memory to a display a predetermined amount of data representing at least one line of an image to be displayed on the display, and for issuing an interrupt following each transfer of the predetermined amount of data; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for sending one first command to the DMA or communications controller and thereafter responsive to receipt of each interrupt for sending a next first command to the DMA or communications controller, and means responsive to receipt of each interrupt for generating a sync signal for the display, to cause the display to display the image represented by the transferred data.

Claim 17

The controller of claim 11 wherein the DMA or communications controller is responsive to each first command by once transferring from the memory to the display a predetermined amount of data representing a line of a frame of the image to be displayed on the display, and the generating means of the processor respond to receipt of each interrupt by generating a horizontal sync signal for the display, the sending means of the processor respond to receipt of each interrupt by sending the next first command to the DMA or communications controller, and the generating means of the processor further respond to receipt of every Nth interrupt, where N is the number of the lines in one said frame of the image, by generating a vertical sync signal for the display.

Claim 18

A display controller comprising: a DMA or communications controller including means for retrieving data from a memory that stores data representing at least one line of an image to be displayed on a display, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit-serial data stream when retrieved data are being transmitted at the first output port, and a third output port for transmitting a signal to a sync input port of the display; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for causing the communications controller to periodically retrieve from memory and transmit at the first output port data representing the at least one line of the image, and means for transmitting a sync signal at the third port following each transmission by the first port of data representing the at least one line of the image.

Claim 19

A display controller comprising: a DMA or communications controller including means for retrieving data from a memory that stores data representing at least one line of an image to be displayed on a display, a first output port connected to the retrieving means for transmitting the retrieved data as a bit-serial data stream to a data input port of the display, a second output port for transmitting a bit-clock signal stream to a clock input port of the display in parallel with the bit-serial data stream when retrieved data are being transmitted at the first output port, and a third output port for transmitting a signal to a sync input port of the display; and a programmable processor connected to the DMA or communications controller and programmed to comprise means for causing the communications controller to periodically retrieve from memory and transmit at the first output port data representing the at least one line of the image, and means for transmitting a sync signal at the third port following each transmission by the first port of data representing the at least one line of the image.

Claim 20

The display controller of claim 13 wherein the means for retrieving comprise means for retrieving data from a memory that stores data representing lines of an image frame to be displayed on a display; the DMA or communications controller further includes a fourth output port for transmitting a signal to a vertical sync input port of the display; and the causing means of the processor cause the communications controller to periodically retrieve from memory and transmit at the first output port data representing a line of the image frame, and the transmitting means of the processor transmit a horizontal sync signal at the third port following each transmission by the first port of data representing a line of the image frame, and cause the fourth port to transmit a vertical sync signal following transmissions by the first port of data representing a last line of the image frame.

Claim 21

The display controller of claim 14 wherein the communications controller further includes a fifth output port for transmitting a signal to an alternating signal input port of the display; and wherein the programmable processor is further programmed to comprise means for causing the fifth port to transmit a signal, and to invert the signal being transmitted following transmissions by the first port of data representing the last line of the image frame.

Claim 22

The display controller of claim 13 wherein the first output port is operable in transparent mode for transmitting the retrieved data as an unformatted bit-serial data stream.

Claim 23

The display controller of claim 13 wherein the second output port comprises: a fourth output port for transmitting a bit-clock signal stream in parallel with the bit-serial data stream transmitted at the first output port; a fifth output port for transmitting a ready-to-send signal when retrieved data are being transmitted at the first output port; and gating means having input ports connected to the fourth and fifth output ports and having the second output port, for receiving the bit-clock signal stream from the fourth output port and transmitting the received signal stream at the second output port only when it receives the ready-to-send signal from the fifth output port.

Claim 24

The display controller of claim 17 wherein the gating means comprise: nor-function means having input ports connected to the fourth and fifth output ports and having the second output port, for receiving the bit-clock signal stream from the fourth output port, inverting the received signal stream, and transmitting the inverted signal stream at the second output port only when it receives the ready-to-send signal from the fifth output port.

Claim 25

The display controller of claim 13 wherein the communications controller includes means for indicating that transmission of data retrieved from memory has been completed; and the causing means of the programmable processor cause the controller to retrieve from memory and transmit at the first output port data representing a next line of the image frame, in response to indication of transmission completion by the indicating means.

Claim 26

The display controller of claim 13 wherein the communications controller is a direct-memory-access serial-communications controller.

Claim 27

A user telecommunications terminal comprising: means for providing telecommunications functions, including means for communicating with a user; means for interfacing the providing means to a telecommunications link; a display; memory means for storing data representative of an image to be displayed on the display; a DMA or communications controller interconnecting the memory means and the display and supplying the data from the memory means directly to the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and operatively coupled to the providing means and to the interface means and programmed to comprise means for controlling the providing means and the interface means to effect transfer of communications between the user and the telecommunications link, means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals including display synchronization signals to cause the display to display the image represented by the transferred data.

Claim 28

A user telecommunications terminal comprising: means for providing telecommunications functions, including means for communicating with a user; means for interfacing the providing means to a telecommunications link; a display; memory means for storing data representative of an image to be displayed on the display; a DMA or communications controller interconnecting the memory means and the display and supplying the data from the memory means directly to the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and operatively coupled to the providing means and to the interface means and programmed to comprise means for controlling the providing means and the interface means to effect transfer of communications between the user and the telecommunications link, means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals including display synchronization signals to cause the display to display the image represented by the transferred data.

Claim 29

The terminal of claim 21 wherein: the control signals generated by the generating means of the processor comprise horizontal and vertical sync signals.

Claim 30

A user telecommunications terminal comprising: means for providing telecommunications functions, including means for communicating with a user; means for interfacing the providing means to a telecommunications link; a display; memory means for storing data representative of an image to be displayed on the display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and operatively coupled to the providing means and to the interface means and programmed to comprise means for controlling the providing means and the interface means to effect transfer of communications between the user and the telecommunications link, means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data, wherein: the causing means of the programmable processor sends a command to the DMA or communications controller; the DMA or communications controller responds to each command received from the processor by once transferring from the memory means to the display an amount of data representing one line of the image, and sends an interrupt to the processor following each transfer of the amount of data representing one line; the generating means of the processor responds to receipt of each interrupt by generating a horizontal sync signal; the causing means of the processor responds to receipt of each interrupt by again sending the command to the DMA or communications controller; and the generating means of the processor further responds to receipt of each Nth interrupt, where N is a number of lines in a frame of the image, by generating a vertical sync signal.

Claim 31

A user telecommunications terminal comprising: means for providing telecommunications functions, including means for communicating with a user; means for interfacing the providing means to a telecommunications link; a display; memory means for storing data representative of an image to be displayed on the display; a DMA or communications controller interconnecting the memory means and the display instead of a display controller; and a programmable processor connected to the DMA or communications controller and operatively coupled to the providing means and to the interface means and programmed to comprise means for controlling the providing means and the interface means to effect transfer of communications between the user and the telecommunications link, means for repeatedly causing the DMA or communications controller to transfer the data from the memory means to the display, and means for repeatedly generating control signals to cause the display to display the image represented by the transferred data, wherein: the causing means of the programmable processor sends a command to the DMA or communications controller; the DMA or communications controller responds to each command received from the processor by once transferring from the memory means to the display an amount of data representing one line of the image, and sends an interrupt to the processor following each transfer of the amount of data representing one line; the generating means of the processor responds to receipt of each interrupt by generating a horizontal sync signal; the causing means of the processor responds to receipt of each interrupt by again sending the command to the DMA or communications controller; and the generating means of the processor further responds to receipt of each Nth interrupt, where N is a number of lines in a frame of the image, by generating a vertical sync signal.