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US5222191A
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Fuzzy hardware system
Assignee: NEC Corp
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Filing: 1991-11-08
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Granted: 1993-06-22
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Expires: 2011-11-08
Abstract
Abstract A fuzzy hardware system includes a sampling circuit which carries out sampling of a first membership function in generate a fuzzy set consisting of a plurality of singletons, and an arithmetic circuit which carries out arithmetic processes in accordance with supplied signals each having either characteristic of a pulse width and a number of pulses corresponding to a size of the singletons. In the arithmetic circuit, minimum and maximum arithmetic processes are carried out by AND and OR gates. Such arithmetic processes are carried out by either process of serial, parallel and combinations of serial and parallel.
Inventors
- 👤 Toshio Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:44
CPC Classifications
G; G06; G06N; G06N7/00; G06N7/02; G06N7/04; Y; Y10; Y10S; Y10S706/00; Y10S706/90
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
241 words
A digital fuzzy hardware system comprising: a sampling circuit for sampling fuzzy membership functions so as to generate a fuzzy set consisting of a plurality of singletons each having a magnitude defined on a time axis by one of a pulse width and a pulse number of a pulse train; and a fuzzy logic circuit connected to said sampling circuit for receiving therefrom pulses corresponding to sampled values of a predetermined membership function and a fact information and carrying out an arithmetic process in accordance with said pulses supplied to said logic circuit; said fuzzy logic circuit comprising: a first MIN circuit for carrying out a minimum arithmetic process to obtain a minimum value from a pair of said singletons of corresponding membership functions, a first MAX circuit for carrying out a maximum arithmetic process to obtain a maximum value from a result of said minimum arithmetic process carried out by said first MIN circuit, a second MIN circuit for carrying out a minimum arithmetic process to obtain a minimum value from a result of said maximum arithmetic process carried out by said first MAX circuit, an α-cutting circuit for α-cutting one of the membership functions by a result of said minimum arithmetic process carried out by said second MIN circuit, and a second MAX circuit for carrying out a maximum arithmetic process to obtain a maximum value from a result of an α-cut operation carried out by said α-cutting circuit.
Claim 2
Dependent Claim
241 words
A digital fuzzy hardware system comprising: a sampling circuit for sampling fuzzy membership functions so as to generate a fuzzy set consisting of a plurality of singletons each having a magnitude defined on a time axis by one of a pulse width and a pulse number of a pulse train; and a fuzzy logic circuit connected to said sampling circuit for receiving therefrom pulses corresponding to sampled values of a predetermined membership function and a fact information and carrying out an arithmetic process in accordance with said pulses supplied to said logic circuit; said fuzzy logic circuit comprising: a first MIN circuit for carrying out a minimum arithmetic process to obtain a minimum value from a pair of said singletons of corresponding membership functions, a first MAX circuit for carrying out a maximum arithmetic process to obtain a maximum value from a result of said minimum arithmetic process carried out by said first MIN circuit, a second MIN circuit for carrying out a minimum arithmetic process to obtain a minimum value from a result of said maximum arithmetic process carried out by said first MAX circuit, an α-cutting circuit for α-cutting one of the membership functions by a result of said minimum arithmetic process carried out by said second MIN circuit, and a second MAX circuit for carrying out a maximum arithmetic process to obtain a maximum value from a result of an α-cut operation carried out by said α-cutting circuit.
Claim 3
Dependent Claim
38 words
A digital fuzzy hardware system according to claim 1, wherein: said fuzzy logic circuit further comprises a circuit for calculating center of gravity of a result of said maximum arithmetic process carried out by said second MAX circuit.
Claim 4
Dependent Claim
35 words
A digital fuzzy hardware system according to claim 1, wherein: each of said first and second MIN circuits is an AND gate, and each of said first and second MAX circuits is an OR gate.
Claim 5
Dependent Claim
31 words
A digital fuzzy hardware system according to claim 1, wherein: said fuzzy logic circuit carries out said arithmetic process by one of serial, parallel and combination of serial and parallel process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |