US5222042A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic semiconductor memory device for raising voltage level of a word line
Assignee: Mitsubishi Electric Corp
•
Filing: 1991-09-04
•
Granted: 1993-06-22
•
Expires: 2011-09-04
Abstract
Abstract A dynamic semiconductor memory device capable of boosting a word line of a memory cell array higher than supply voltage, and methods of boosting the level of the word line are disclosed. The dynamic RAM of the present invention includes a RAS (Row Address Strobe) buffer, an address buffer, a write buffer, a word line driving signal generating circuit, a first word line boost circuit and a second word line boost circuit. The word line driving signal generating circuit boosts the word line to the supply voltage in response to a row address strobe signal from the RAS buffer. The first word line boost circuit boosts the word line to be higher than the supply voltage. The second word line boost circuit again boosts the word line in response to a write enable signal from the write buffer. In this manner, unsuccessful writing due to leakage of capacitance can be suppressed.
Inventors
- 👤 Tetsuchiro Ichiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4085
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
180 words
A dynamic semiconductor memory device including at least one memory cell array including memory cells arranged at cross sections of a plurality of word lines and a plurality of bit lines, comprising: state signal receiving means for receiving an external control signal for controlling storage state of said memory device; address receiving means for receiving an external address signal for addressing said memory device; write control signal receiving means for receiving an external write control signal for controlling writing to said memory device; word line driving signal generating means responsive to the control signal from said state signal receiving means for generating a driving signal for driving a word line; first boosting means for boosting said driving signal to be higher than supply voltage; second boosting means responsive to said write control signal for boosting again said driving signal; and a decoder connected to said memory cell array for decoding the address signal from said address receiving means for supplying the driving signal boosted by said second boosting means to the word line corresponding to the address signal in writing.
Claim 2
Dependent Claim
180 words
A dynamic semiconductor memory device including at least one memory cell array including memory cells arranged at cross sections of a plurality of word lines and a plurality of bit lines, comprising: state signal receiving means for receiving an external control signal for controlling storage state of said memory device; address receiving means for receiving an external address signal for addressing said memory device; write control signal receiving means for receiving an external write control signal for controlling writing to said memory device; word line driving signal generating means responsive to the control signal from said state signal receiving means for generating a driving signal for driving a word line; first boosting means for boosting said driving signal to be higher than supply voltage; second boosting means responsive to said write control signal for boosting again said driving signal; and a decoder connected to said memory cell array for decoding the address signal from said address receiving means for supplying the driving signal boosted by said second boosting means to the word line corresponding to the address signal in writing.
Claim 3
Dependent Claim
45 words
A dynamic semiconductor memory device according to claim 1, wherein said state signal receiving means includes means responsive to an external control signal for generating a row address strobe signal for controlling said address receiving means, said first boosting means and said second boosting means.
Claim 4
Dependent Claim
32 words
A dynamic semiconductor memory device according to claim 1, wherein said address signal includes a signal for selecting a desired memory cell array out of said at least one memory cell array.
Claim 5
Dependent Claim
79 words
A dynamic semiconductor memory device according to claim 3, wherein said word line driving signal generating means includes selecting means for selecting a desired memory cell array out of said at least one memory cell array based on said address signal and said state control signal, a word line driving line connected to the memory cell array selected by said selecting means, and charging means for charging said word line driving line to a potential of the driving signal.
Claim 6
Dependent Claim
61 words
A dynamic semiconductor memory device according to claim 1, wherein said first boosting means includes delay means for providing a delay of a prescribed time period to the driving signal generated by said word line driving signal generating means, and first capacitor means charged by said driving signal and discharged in response to the driving signal delayed by said delay means.
Claim 7
Dependent Claim
21 words
A dynamic semiconductor memory device according to claim 1, wherein said delay means includes a plurality of inverters connected in series.
Claim 8
Dependent Claim
47 words
A dynamic semiconductor memory device according to claim 6, wherein said second boosting means includes second capacitor means having one end connected to said word line driving line, and write signal supplying means for supplying a write signal to the other end of said second capacitor means.
Claim 9
Dependent Claim
44 words
A dynamic semiconductor memory device according to claim 7, wherein said second boosting means includes switching means connected between the other end of said second capacitor means and the ground for switching in response to the state signal from said state signal receiving means.
Claim 10
Dependent Claim
82 words
A dynamic semiconductor memory device according to claim 7, wherein said write signal supply means includes an inverter connected to the delay means of said first boosting means, logic gate means receiving an output signal from said inverter and said write signal, and transmitting means connected between an output of the logic gate means and the other end of the second capacitor means, responsive to said write signal, for transmitting the output from the logic gate means to said second capacitor means.
Claim 11
Independent Claim
152 words
A method of boosting a word line of a dynamic semiconductor memory device including at least one memory cell array including memory cells arranged at crossings of a plurality of word lines and a plurality of bit lines, comprising the steps of: receiving an external control signal for controlling storage state of said memory device; receiving an external address signal for addressing said memory device; receiving an external write control signal for controlling writing to said memory device; generating a driving signal for driving the word line, in response to the control signal from said state signal receiving means; boosting said driving signal to be higher than supply voltage; boosting again said driving signal in response to said write control signal; and decoding the address signal from said address receiving means and supplying the driving signal which has been boosted again to the word line corresponding to the address signal in writing.
Claim 12
Independent Claim
152 words
A method of boosting a word line of a dynamic semiconductor memory device including at least one memory cell array including memory cells arranged at crossings of a plurality of word lines and a plurality of bit lines, comprising the steps of: receiving an external control signal for controlling storage state of said memory device; receiving an external address signal for addressing said memory device; receiving an external write control signal for controlling writing to said memory device; generating a driving signal for driving the word line, in response to the control signal from said state signal receiving means; boosting said driving signal to be higher than supply voltage; boosting again said driving signal in response to said write control signal; and decoding the address signal from said address receiving means and supplying the driving signal which has been boosted again to the word line corresponding to the address signal in writing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |