Data amplifying system in semiconductor memory device

Claim 2

A data amplifying system in a semiconductor memory, comprising: current mirror circuit means for receiving, via a data bus, an input signal corresponding to data read out from a memory cell via a pair of bit lines and for amplifying said input signal, said current mirror circuit means being connected to a power supply line having a power supply voltage; amplitude limiting means for receiving an operation voltage and for limiting an amplitude of said input signal on said data bus to a predetermined potential range on the basis of said operation voltage; and bit line reset potential generating means, coupled to said bit lines and said amplitude limiting means, for generating a bit line reset potential to said bit lines and said amplitude limiting means, wherein a bit line reset voltage is lower than said power supply voltage supplied from said power supply line and serving as said operation voltage applied to said amplitude limiting means.

Claim 3

A data amplifying system as claimed in claim 1, wherein: said bit line reset potential generating means comprises means for generating said bit line reset potential from said power supply voltage; and said operation voltage corresponding to said bit line reset potential is approximately half of said power supply voltage.

Claim 4

A data amplifying system as claimed in claim 1, wherein said amplitude limiting means comprises: a first field effect transistor having a drain receiving said operation voltage lower than said power supply voltage, a source connected to a first line of said data bus, and a gate receiving a predetermined enable signal; and a second field effect transistor having a drain receiving said operation voltage, a source coupled to a second line of said data bus, and a gate receiving said predetermined enable signal.

Claim 5

A data amplifying system as claimed in claim 1, wherein said bit line reset potential generating means comprises: a first transistor having a source receiving said power supply voltage, a gate receiving a predetermined enable signal, and a drain; a second transistor having a source receiving said power supply voltage, a gate grounded, and a drain; reference voltage generating means for generating a reference voltage approximately half said power supply voltage from said power supply voltage; a third transistor having a source coupled to the drains of said first and second transistors, a gate receiving said reference voltage, and a drain; a fourth transistor having a source coupled to the drains of said first and second transistors, a gate, and a drain; a fifth transistor having a drain coupled to the drain of said third transistor, a source grounded, and a gate; a sixth transistor having a drain coupled to the drain of said fourth transistor, a source grounded, and a gate connected to the gate of said fifth transistor, the gates of said fifth and sixth transistors being connected to the drain of one of the fifth and sixth transistors; and a seventh transistor having a source receiving said power supply voltage, a gate connected to the drain of one of said fifth and sixth transistors, and a drain coupled to the gate of the fourth transistor, said bit line reset potential being obtained at the drain of said seventh transistor.

Claim 6

A data amplifying system as claimed in claim 1, wherein said current mirror circuit means comprises: a first transistor having a source receiving said power supply voltage, a drain and a gate; a second transistor having a source receiving said power supply voltage, a gate connected to the gate of said first transistor, and a drain; a third transistor having a drain connected to the drain of said first transistor, a gate receiving a first component of said input signal, and a source; a fourth transistor having a drain connected to the drain of said second transistor, a gate receiving a second component of said input signal, and a source; and a fifth transistor having a drain connected to the sources of said third and fourth transistors, a gate receiving a predetermined enable signal, and a source grounded, amplified output signals being obtained at the drains of said third and fourth transistors.

Claim 7

A data amplifying system in a semiconductor memory comprising: current mirror circuit means for receiving, via a data bus, an input signal corresponding to data read out from a memory cell via a pair of bit lines and for amplifying said input signal, said current mirror circuit means operating on the basis of a power supply voltage; amplitude limiting means for receiving an operation voltage and for limiting an amplitude of said input signal on said data bus to a predetermined potential range on the basis of said operation voltage; and generating means, coupled to said amplitude limiting means, for generating said operation voltage from said power supply voltage, said operation voltage being approximately half said power supply voltage.

Claim 8

A data amplifying system in a semiconductor memory comprising: current mirror circuit means for receiving, via a data bus, an input signal corresponding to data read out from a memory cell via a pair of bit lines and for amplifying said input signal, said current mirror circuit means operating on the basis of a power supply voltage; amplitude limiting means for receiving an operation voltage and for limiting an amplitude of said input signal on said data bus to a predetermined potential range on the basis of said operation voltage; and generating means, coupled to said amplitude limiting means, for generating said operation voltage from said power supply voltage, said operation voltage being approximately half said power supply voltage.