Floating-point processor for performing an arithmetic operation on fixed-point part data with high speed rounding of a result

Claim 1

A floating-point processor for performing addition and subtraction of two floating-point numbers, said floating-point processor comprising: a carry saving adder-subtracter for generating carry data and sum data by performing addition and subtraction of a first fixed-point part of the floating-point number having a greater exponent part and a second fixed-point part, which is aligned with the first fixed-point part by being shifted right, of the other floating-point number having a smaller exponent part according to following equations: (i) in case where an addition is performed, a.sub.i +b.sub.i =2c.sub.i +s.sub.i ; (ii) in case where a subtraction is performed and the carry data is positive, a.sub.i +b.sub.i =2c.sub.i -s.sub.i ; (iii) in case where a subtraction is performed and the carry data is negative, a.sub.i -b.sub.i =-2c.sub.i +s.sub.i ; where i is an integer greater than zero; a i denotes a value held at an ith digit of the first fixed-point part; b i denotes a value held at an ith digit of the second fixed-point part; c i denotes a value held at an ith digit of the carry data; and s i denotes a value held at an ith digit of the sum data; a rounding-carry generating circuit for generating a first rounding-carry, of which the value in case of rounding a result of addition or subtraction between the first and second fixed-point parts to a higher order digit is in agreement with the value in case of rounding the result of addition or subtraction between the first and second fixed-point parts to a lower order digit, from a rounding-mode signal indicating the direction in which a result of addition or subtraction between the first and second fixed-point parts is rounded, and low-order digits of the first and second fixed-point parts and for generating a second rounding-carry in each of the cases of rounding the result of addition or subtraction between the first and second fixed-point parts to a higher order digit and or rounding the result of addition or subtraction between the first and second fixed-point parts to a lower order digit; an adder-subtracter for outputting a first result of addition or subtraction between data, which is obtained by adding the first rounding-carry to the least significant digit of the carry data, and the sum data and for outputting a second result of adding 1 to or subtracting 1 from the first result; an inversion circuit for outputting a logical inversion of all digits of the second result; and a selection circuit for selecting and outputting one of the first result, the second result and an output of the inversion circuit on the basis of high-order digits of the first and second results and the second rounding-carry.