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US5221911A Expired / Lapsed US ⏱️ 0.0 years remaining

Receiver having pll frequency synthesizer with rc loop filter

Assignee: US Philips Corp
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Filing: 1992-06-12
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Granted: 1993-06-22
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Expires: 2012-06-12
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Abstract

Abstract A receiver having an RF section, a mixer stage and a signal processing stage, the mixer stage receiving a mixing frequency from a frequency synthesis circuit which includes a phase-locked loop provided with a phase detection device having a current output, a loop filter including a π-shaped RC network having an input shunt path and an output shunt path which are connected to respective ends of a series resistor incorporated in a series path, and to ground, and include first and second capacitances, respectively, and with a voltage-controlled oscillator, a reference frequency being applied to the phase detection device. In order to prevent the use of active filter circuits in the phase-locked loop of such a receiver, the second capacitance is chosen to be at least twice as large as the first capacitance, the series resistance is chosen to be smaller than the output impedance of the phase detection device and the output shunt path of the loop filter is provided with an RC phase shift member for reducing the phase shift of the second capacitance in the output shunt path.

Inventors

  • 👤 Wolfdietrich G. Kasperkovitz
  • 👤 Hubertus H. M. Vereijken

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 21:52
CPC Classifications
H; H03; H03J; H03J5/00; H03J5/02; H03J5/0245; H03J5/0272; H04; H04B; H04B1/00; H04B1/06; H04B1/10; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/107; H03L7/1075; H03L7/085; H03L7/089; H03L7/0891; H03L7/16; H03L7/18; H03L7/183

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 159 words
A receiver comprising an RF section, a mixer stage and a signal processing section, said mixer stage receiving a mixing frequency from a frequency synthesis circuit which comprises phase-locked loop provided with a phase detection device having a current output, a loop filter comprising a π-shaped RC network having an input shunt path and an output shunt path which are connected to respective ends of a series resistor, incorporated in a series path and to ground and comprise first and second capacitances, respectively, and with a voltage-controlled oscillator, a reference frequency being applied to said phase detection device, characterized in that the second capacitance is at least twice as large as the first capacitance, the series resistance is smaller than the output impedance of the phase detection device and the output shunt path of the loop filter is provided with an RC phase shift member for reducing the phase shift of the second capacitance in the output shunt path.
Claim 2
Dependent Claim 159 words
A receiver comprising an RF section, a mixer stage and a signal processing section, said mixer stage receiving a mixing frequency from a frequency synthesis circuit which comprises phase-locked loop provided with a phase detection device having a current output, a loop filter comprising a π-shaped RC network having an input shunt path and an output shunt path which are connected to respective ends of a series resistor, incorporated in a series path and to ground and comprise first and second capacitances, respectively, and with a voltage-controlled oscillator, a reference frequency being applied to said phase detection device, characterized in that the second capacitance is at least twice as large as the first capacitance, the series resistance is smaller than the output impedance of the phase detection device and the output shunt path of the loop filter is provided with an RC phase shift member for reducing the phase shift of the second capacitance in the output shunt path.
Claim 3
Dependent Claim 32 words
A receiver as claimed in claim 1, characterized in that the RC member comprises a parallel arrangement of a resistor and a capacitance which is arranged in series with the second capacitance.
Claim 4
Dependent Claim 32 words
A receive as claimed in claim 1, characterized in that the RC member comprises a series arrangement of a resistor and a capacitance which is arranged in parallel with the second capacitance.
Claim 5
Dependent Claim 24 words
A receiver as claimed in claim 1, characterized in that a pair of anti-parallel connected diodes is arranged in parallel across the series resistor.
Claim 6
Dependent Claim 24 words
A receiver as claimed in claim 2, characterized in that a pair of anti-parallel connected diodes is arranged in parallel across the series resistor.

References Cited (Backward Citations)

US3316497A Cited
US3810046A Cited
US4837853A Cited
US4952888A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-06-21 1996-12-21 1997-06-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-06-21 2000-12-21 2001-06-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-06-21 2004-12-21 2005-06-22 $7700.00 Window Closed / Lapsed

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