Circuitry and method for variable single transition counting

Claim 2

Circuitry for variable single transition counting, comprising: a count line for providing a count signal; a direction control line for outputting a direction control bit; a significant bit line for outputting a significant bit; a single transition counter coupled to said count line and to said direction control line and operable to increment a first single transition count in response to said count signal and to said direction control bit having an incrementing logic state, and further operable to decrement said first single transition count in response to said count signal and to said direction control bit having a decrementing logic state, wherein said first single transition count and said significant bit together form a second single transition count; comparison circuitry coupled to said significant bit line and to said single transition counter for outputting a comparison signal in response to said second single transition count being equal to a preselected value; and toggling circuitry coupled to said comparison circuitry, to said single transition counter and to said significant bit line for toggling said direction control bit and said significant bit in response to said comparison signal, such that a value of said second single transition count may be changed in response to said preselected value.

Claim 3

The circuitry of claim 1 wherein said toggling circuitry is operable to toggle said direction control bit and said significant bit without modifying said first single transition count.

Claim 4

The circuitry of claim 1 wherein said toggling circuitry is further coupled to said count line and is operable to toggle said direction control bit and said significant bit in response to said comparison signal and to a positive edge transition of said count signal.

Claim 5

The circuitry of claim 1 wherein said toggling circuitry toggles said direction control bit and said significant bit in response to said comparison signal such that said direction control bit and said significant bit are toggled when said second single transition count is equal to said preselected value.

Claim 6

The circuitry of claim 4 wherein said toggling circuitry is further coupled to said count line and wherein said comparison circuitry outputs said comparison signal to said toggling circuitry before a next count signal on said count line, such that said direction control bit and said significant bit are toggled after said next count signal when said second single transition count is equal to said preselected value.

Claim 7

The circuitry of claim 1 wherein said toggling circuitry toggles said direction control bit and said significant bit in response to said comparison signal such that said direction control bit and said significant bit are toggled when said second single transition count is equal to a successive value following said preselected value.

Claim 8

The circuitry of claim 6 wherein said toggling circuitry is further coupled to said count line and wherein said comparison circuitry outputs said comparison signal to said toggling circuitry after a first next count signal on said count line, such that said direction control bit and said significant bit are toggled after a second next count signal on said count line when said second single transition count is equal to a successive value following said preselected value.

Claim 9

The circuitry of claim 1 wherein said direction control bit is output by a latch.

Claim 10

The circuitry of claim 1 wherein said significant bit is output by a latch.

Claim 11

The circuitry of claim 9 wherein said toggling circuitry is further coupled to said count line and wherein said toggling circuitry toggles said significant bit without modifying said first single transition count by disabling said count signal from said single transition counter and by enabling said count signal to said latch.

Claim 12

The circuitry of claim 10 wherein said toggling circuitry disables said count signal from said single transition counter and enables said count signal to said latch in response to a negative edge transition of said count signal.

Claim 13

The circuitry of claim 1 wherein said comparison circuitry is operable to output said comparison signal in response to said second single transition count being equal to a second preselected value, such that said value of said second single transition count may be changed in response to said preselected value and to said second preselected value

Claim 14

The circuitry of claim 1 and further comprising latch circuitry coupled to said comparison circuitry for latching said preselected value.

Claim 15

The circuitry of claim 13 wherein said latch circuitry is operable to change said preselected value in response to a load signal.

Claim 16

The circuitry of claim 1 wherein only one bit of said second single transition count is modified in response to each count signal on said count line.

Claim 17

A first-in-first-out memory system, comprising: a plurality of memory locations each for storing data; a first count line for outputting a first count signal in response to data being written to one of said memory locations; a write index counter coupled to said first count line for incrementing a write index in response to each said first count signal; a second count line for outputting a second count signal in response to data being read from one of said memory locations; and a read index counter coupled to said second count line for incrementing a read index in response to each said second count signal, wherein said write index counter and said read index counter each comprise an associated variable single transition counter comprising: a direction control line for outputting a direction control bit; a significant bit line for outputting a significant bit; a single transition counter coupled to an associated one of said first and second count lines and to said direction control line and operable to increment a first ingle transition count in response to said count signal of said associated count line and to said direction control bit having an incrementing logic state, and further operable to decrement said first single transition count in response to said count signal and to said direction control bit having a decrementing logic state, wherein said first single transition count and said significant bit together form a second single transition count; comparison circuitry coupled to said significant bit line and to said single transition counter for outputting a comparison signal in response to said second single transition count being equal to a preselected value; and toggling circuitry coupled to said comparison circuitry, to said single transition counter and to said significant bit line for toggling said direction control bit and said significant bit in response to said comparison signal, such that a value of said second single transition count may be changed in response to said preselected value.

Claim 18

A first-in-first-out memory system, comprising: a plurality of memory locations each for storing data; a first count line for outputting a first count signal in response to data being written to one of said memory locations; a write index counter coupled to said first count line for incrementing a write index in response to each said first count signal; a second count line for outputting a second count signal in response to data being read from one of said memory locations; and a read index counter coupled to said second count line for incrementing a read index in response to each said second count signal, wherein said write index counter and said read index counter each comprise an associated variable single transition counter comprising: a direction control line for outputting a direction control bit; a significant bit line for outputting a significant bit; a single transition counter coupled to an associated one of said first and second count lines and to said direction control line and operable to increment a first ingle transition count in response to said count signal of said associated count line and to said direction control bit having an incrementing logic state, and further operable to decrement said first single transition count in response to said count signal and to said direction control bit having a decrementing logic state, wherein said first single transition count and said significant bit together form a second single transition count; comparison circuitry coupled to said significant bit line and to said single transition counter for outputting a comparison signal in response to said second single transition count being equal to a preselected value; and toggling circuitry coupled to said comparison circuitry, to said single transition counter and to said significant bit line for toggling said direction control bit and said significant bit in response to said comparison signal, such that a value of said second single transition count may be changed in response to said preselected value.

Claim 19

The system of claim 16 and further comprising comparison circuitry for comparing said write index against said read index.

Claim 20

The system of claim 17 and further comprising indication circuitry coupled to said comparison circuitry for outputting a full flag in response to said write index counter incrementing said write index to equal said read index.

Claim 21

The system of claim 17 and further comprising indication circuitry coupled to said comparison circuitry for outputting an empty flag in response to said read index counter incrementing said read index to equal said write index.

Claim 24

The method of claim 20 wherein said toggling step comprises the step of toggling said direction control bit and said significant bit without modifying said first single transition count.

Claim 25

The method of claim 21 wherein said toggling step comprises the steps of: disabling said count signal from a single transition counter which outputs said first single transition count; and enabling said count signal to a latch which outputs said significant bit.

Claim 26

The method of claim 22 wherein said disabling step comprises the step of disabling said count signal from said single transition counter in response to a negative edge transition of said count signal, and wherein said enabling step comprises the step of enabling said count signal to said latch in response to said negative edge transition of said count signal.

Claim 27

The method of claim 20 wherein said toggling step comprises the step of toggling said direction control bit and said significant bit in response to said comparison signal and to a positive edge transition of said count signal.

Claim 28

The method of claim 20 wherein said toggling step comprises the step of toggling said direction control bit and said significant bit in response to said comparison signal such that said direction control bit and said significant bit are toggled when said second single transition count is equal to said preselected value.

Claim 29

The method of claim 25 wherein said comparing step comprises the step of outputting said comparison signal before a next count signal on said count line, such that said direction control bit and said significant bit are toggled after said next count signal when said second single transition count is equal to said preselected value.

Claim 30

The method of claim 20 wherein said toggling step comprises the step of toggling said direction control bit and said significant bit in response to said comparison signal such that said direction control bit and said significant bit are toggled when said second single transition count is equal to a successive value following said preselected value.

Claim 31

The method of claim 27 wherein said comparing step comprises the step of outputting said comparison signal after a first next count signal on said count line, such that said direction control bit and said significant bit are toggled after a second next count signal on said count line when said second single transition count is equal to a successive value following said preselected value.

Claim 32

The method of claim 20 wherein said comparing step comprises the step of outputting said comparison signal in response to said second single transition count being equal to a second preselected value, such that said value of said second single transition count may be changed in response to said preselected value and to said second preselected value.

Claim 33

The method of claim 20 and further comprising the step of changing said preselected value in response to a load signal.

Claim 34

The method of claim 20 wherein only one bit of said second single transition count is modified in response to each count signal on said count line.