Two-way handshake circuit and method for communication between processors

Claim 2

A handshake circuit for coordinating and regulating the exchange of data messages between a first and a second data processor, each having memory and control software associated therewith, the handshake circuit comprising: a first input/output means within the first data processor for receiving signals and transmitting signals, the control software associated with the first data processor configuring the first input/output means in one of a signal receiving mode and a signal transmitting mode; a second input/output means within the second data processor for receiving signals and transmitting signals, the control software associated with the second data processor configuring the second input/output means in one of a signal receiving mode and a signal transmitting mode; and self-latching circuit means connecting the first and the second input/output means for storing signals transmitted between the first data processor and the second data processor, wherein the first input/output means, the second input/output means and the self-latching circuit means are operable for bidirectionally regulating data transfer between the first data processor and the second data processor.

Claim 3

The handshake circuit of claim 1 wherein the first and second input/output means comprises tri-state input/output port means.

Claim 4

The handshake circuit of claim 1 wherein the self-latching circuit means comprises: a first branch connected between the first and second input/output means including a first amplifier connected in series with a first resistor so as to allow signals to be transmitted in only one direction; and a second branch connected in parallel with the first branch and including a second amplifier connected in series with a second resistor so as to allow signals to be transmitted in a direction opposite to the one direction.

Claim 5

The handshake circuit of claim 1 wherein the self-latching circuit means comprises: a first branch connected between the first and second input/output means including a first invertor connected in series with a first resistor so as to allow signals to be transmitted in only one direction; and a second branch connected in parallel with the first branch and including a second invertor connected in series with a second resistor so as to allow signals to be transmitted in a direction opposite to the one direction.

Claim 6

The handshake circuit of claim 2 wherein the self-latching circuit means comprises: a first branch connected between the first and second input/output means including a first amplifier connected in series with a first resistor so as to allow signals to be transmitted in only one direction; and a second branch connected in parallel with the first branch and including a second amplifier connected in series with a second resistor so as to allow signals to be transmitted in a direction opposite to the one direction.

Claim 7

A handshake circuit of claim 2 wherein the self-latching circuit means comprises: a first branch connected between the first and second input/output means including a first invertor connected in series with a first resistor so as to allow signals to be transmitted in only one direction; and a second branch connected in parallel with the first branch and including a second invertor connected in series with a second resistor so as to allow signals to be transmitted in a direction opposite to the one direction.

Claim 8

In a communication system for the transmission of data between a first and a second processor via a data bus, each processor having memory and control software, a method for coordinating and regulating the exchange of data between the first and the second processors comprising: (a) providing a first tri-state input/output port at the first processor; a second tri-state input/output port at the second processor and a self-latching handshake circuit interconnecting the first and the second tri-state input/output ports, wherein the first tri-state input/output port, the second tri-state input/output port and the self-latching handshake circuit are operable for bidirectionally regulating data transfer between the first processor and the second processor; (b) initialing both processors, via their respective control software, to place their respective tri-state input/output ports in a high impedance state enabling either processor to monitor a signal latched to the handshake circuit; (c) causing either one of the processors, via its respective control software, to set its respective tri-state input/output port to a low impedance level for outputting a handshake signal of a first logic level onto the handshake circuit whenever the one processor is ready to receive data on the data bus and thereafter returning the respective tri-state input/output port to a high impedance level; and (d) causing either one of the processors, via its respective control software, to set its respective tri-state input/output port to a low impedance level for outputting a handshake signal of a second logic level onto the handshake circuit whenever the one processor is not ready to receive data on the data bus and thereafter returning the respective tri-state input/output port to a high impedance level.

Claim 9

In a communication system for the transmission of data between a first and a second processor via a data bus, each processor having memory and control software, a method for coordinating and regulating the exchange of data between the first and the second processors comprising: (a) providing a first tri-state input/output port at the first processor; a second tri-state input/output port at the second processor and a self-latching handshake circuit interconnecting the first and the second tri-state input/output ports, wherein the first tri-state input/output port, the second tri-state input/output port and the self-latching handshake circuit are operable for bidirectionally regulating data transfer between the first processor and the second processor; (b) initialing both processors, via their respective control software, to place their respective tri-state input/output ports in a high impedance state enabling either processor to monitor a signal latched to the handshake circuit; (c) causing either one of the processors, via its respective control software, to set its respective tri-state input/output port to a low impedance level for outputting a handshake signal of a first logic level onto the handshake circuit whenever the one processor is ready to receive data on the data bus and thereafter returning the respective tri-state input/output port to a high impedance level; and (d) causing either one of the processors, via its respective control software, to set its respective tri-state input/output port to a low impedance level for outputting a handshake signal of a second logic level onto the handshake circuit whenever the one processor is not ready to receive data on the data bus and thereafter returning the respective tri-state input/output port to a high impedance level.