EPROM source bias circuit with compensation for processing characteristics

Claim 2

Circuitry for improving the programming efficiency of a floating gate transistor when it is programmed by hot electron programming techniques during a programming cycle, the transistor having respective gate, drain and source nodes, the circuitry comprising: a reference voltage generator for generating a reference voltage during said programming cycle, said reference voltage being process-dependent on the conductivity of said floating gate transistor, wherein said reference voltage varies in dependence on the programming characteristics of said floating gate transistor; and voltage biasing means responsive to said reference voltage for biasing the voltage on said source node during programming at a low source voltage when said transistor conductivity is low and at a higher source voltage when said transistor conductivity is high, wherein the drain-to-source voltage of the transistor being programmed is high when said transistor conductivity is low, and low when said transistor conductivity is high.

Claim 3

The circuitry of claim 1 wherein said voltage biasing means comprises a parallel connection of a passive resistance and an active resistance element, said active resistance element responsive to said reference voltage to provide a decreased resistance as said reference voltage increases.

Claim 4

The circuitry of claim 1 wherein said floating gate transistor comprises an electrically programmable read only memory integrated circuit device.

Claim 5

The circuit of claim 3 wherein said EPROM device comprises a plurality of virtually identical floating gate transistors arranged in an array comprising array sections, each array section comprising one or more floating gate transistors, and said voltage biasing means comprises one active bias element for each array section, and wherein said reference voltage generator provides a common reference voltage to each active bias element.

Claim 6

The circuitry of claim 1 wherein said voltage biasing means comprises a voltage source circuit.

Claim 7

The circuitry of claim 1 wherein said voltage biasing means comprises a metal-oxide-semiconductor (MOS) transistor device having a gate, drain and source, the source of said MOS transistor device coupled to the source of the floating gate transistor, said reference voltage being applied to the gate of said MOS transistor device to control an impedance across the source to drain of said MOS transistor device to control the voltage on said source node.

Claim 8

The circuitry of claim 6 wherein said voltage biasing means further comprises a passive resistance device connected in series with said MOS transistor, whereby an impedance across the voltage biasing means is an impedance of the MOS transistor and the passive resistance device.

Claim 9

The circuitry of claim 1 wherein said generator includes a mirror floating gate transistor whose conductivity tracks that of the floating gate transistor being programmed, said reference voltage being dependent on the conductivity of said mirror transistor.

Claim 10

The circuitry of claim 8 wherein said generator comprises means for generating a reference current which is divided between two parallel circuit branches, a first branch comprising a substantially fixed resistance element, and the second element comprising said mirror floating gate transistor, said mirror transistor being gated to the conductive state during the programming cycle, wherein said reference current divides between said two parallel circuit branches in a ratio dependent on the conductivity of said mirror transistor.

Claim 11

The circuitry of claim 9 wherein said reference voltage is developed across said two parallel circuit branches such that as the conductivity of said mirror transistor increases, the reference voltage decreases, and as the conductivity of said mirror transistor decreases, the reference voltage increases.

Claim 12

The circuitry of claim 1 wherein said voltage biasing means is operable to bias the voltage on said transistor source node only during the programming cycle for programming said floating gate transistor.

Claim 13

The circuitry of claim 11 further comprising means for coupling the source of said floating gate transistor to ground except during the programming cycle so that said circuitry does not affect the operation of said floating gate transistor except during the programming cycle.

Claim 14

The circuitry of claim 12 wherein said coupling means comprises an MOS transistor coupled source-to-drain across said voltage biasing means and gated to the conductive state except during the programming cycle for selectively shorting the source of the floating gate transistor to ground except during the programming cycle.

Claim 15

An electrically programmable read only memory (EPROM) integrated circuit device comprising a plurality of EPROM cells, each cell including a floating gate transistor having respective gate, drain and source nodes, which may be selectively programmed during a programming cycle, wherein said cells are arranged in a plurality of columns, each column in turn comprising a plurality of EPROM cells, only one of which cells in a particular column being selected for programming during a given programming cycle, remaining cells in a particular column being characterized as non-selected cells, said EPROM integrated circuit device including circuitry for improving programming efficiency of the floating gate transistors of the EPROM memory cells when they are selectively programmed by hot electron programming techniques, comprising: a reference signal generator for generating a process-dependent reference signal during the programming cycle, said reference signal dependent on the conductivity of a mirror floating gate transistor included in said reference signal generator and whose conductivity tracks that of a selected floating gate transistor being programmed; and voltage biasing means responsive to said reference signal for biasing the voltage on the source node of said selected floating gate transistor being programmed, including means for biasing said source node of said selected floating gate transistor being programmed at a low source voltage when said transistor conductivity of said selected floating gate transistor being programmed is low and for biasing said source node of said selected floating gate transistor being programmed at a higher source voltage when the conductivity of said selected floating gate transistor being programmed is high; wherein the drain-to-source voltage of the selected floating gate transistor being programmed is high when said transistor conductivity of said selected floating gate transistor being programmed is low, and said drain-to-source voltage is low when said transistor conductivity of said selected floating gate transistor being programmed is high.

Claim 16

An electrically programmable read only memory (EPROM) integrated circuit device comprising a plurality of EPROM cells, each cell including a floating gate transistor having respective gate, drain and source nodes, which may be selectively programmed during a programming cycle, wherein said cells are arranged in a plurality of columns, each column in turn comprising a plurality of EPROM cells, only one of which cells in a particular column being selected for programming during a given programming cycle, remaining cells in a particular column being characterized as non-selected cells, said EPROM integrated circuit device including circuitry for improving programming efficiency of the floating gate transistors of the EPROM memory cells when they are selectively programmed by hot electron programming techniques, comprising: a reference signal generator for generating a process-dependent reference signal during the programming cycle, said reference signal dependent on the conductivity of a mirror floating gate transistor included in said reference signal generator and whose conductivity tracks that of a selected floating gate transistor being programmed; and voltage biasing means responsive to said reference signal for biasing the voltage on the source node of said selected floating gate transistor being programmed, including means for biasing said source node of said selected floating gate transistor being programmed at a low source voltage when said transistor conductivity of said selected floating gate transistor being programmed is low and for biasing said source node of said selected floating gate transistor being programmed at a higher source voltage when the conductivity of said selected floating gate transistor being programmed is high; wherein the drain-to-source voltage of the selected floating gate transistor being programmed is high when said transistor conductivity of said selected floating gate transistor being programmed is low, and said drain-to-source voltage is low when said transistor conductivity of said selected floating gate transistor being programmed is high.

Claim 17

The EPROM device of claim 14 wherein said reference signal is a reference voltage, and said voltage biasing means comprises a parallel connection of a passive resistance and an active resistance element, said active resistance element responsive to said reference voltage to provide a decreased resistance as said reference voltage increases.

Claim 18

The EPROM device of claim 14 wherein said mirror transistor is fabricated as a transistor surrounded by other floating gate transistors in a mini-array to emulate the physical characteristics of the floating gate transistor being programmed.

Claim 19

The EPROM device of claim 14 wherein said reference signal generator comprises means for generating a reference current which is divided between two parallel circuit branches, a first branch comprising a substantially fixed resistance element, and the second element comprising said mirror floating gate transistor, said mirror transistor being gated to the conductive state during the programming cycle, wherein said reference current divides between said two parallel circuit branches in a ratio dependent on the conductivity of said mirror transistor.

Claim 20

The EPROM device of claim 17 wherein said reference signal is a reference voltage and said reference voltage is developed across said two parallel circuit branches such that as the conductivity of said mirror transistor increases, the reference voltage decreases, and as the conductivity of said mirror transistor decreases, the reference voltage increases.

Claim 21

The EPROM device of claim 14 wherein said floating gate transistors are virtually identical and arranged in an array comprising array sections, each array section comprising one or more floating gate transistors, and said voltage biasing means comprises one active bias element for each array section.

Claim 22

The EPROM device of claim 14 wherein said reference signal is a reference voltage, and said voltage biasing means comprises a metal-oxide-semiconductor (MOS) transistor device having a gate, drain and source, the drain of said MOS transistor device being coupled to the source nodes of said floating gate transistors, said reference voltage being applied to the gate of said MOS transistor device to control an impedance across the source to drain of said MOS transistors to control the source bias voltage on said floating gate transistors.

Claim 23

The EPROM device of claim 20 wherein said voltage biasing means further comprises a passive resistance device connected in series with said MOS transistor, whereby an impedance across the voltage biasing means is an impedance of the MOS transistor and the passive resistance device.

Claim 24

The EPROM device of claim 14 wherein said voltage biasing means is operable to bias the voltage on said source node of said selected floating gate transistor being programmed only during the programming cycle.

Claim 25

The EPROM device of claim 22 further comprising means for coupling the source nodes of said floating gate transistors to ground except during the programming cycle so that said circuitry does not affect the operation of said floating gate transistors except during the programming cycle.

Claim 26

The EPROM device of claim 23 wherein said coupling means comprises a metal-oxide-semiconductor (MOS) transistor coupled source-to-drain across said voltage biasing means and gated to the conductive state except during the programming cycle for selectively shorting the source nodes of said floating gate transistors to ground except during the programming cycle.