US5218567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Match detection circuit for cache memory apparatus
Assignee: Hitachi Ltd
•
Filing: 1991-11-07
•
Granted: 1993-06-08
•
Expires: 2011-11-07
Abstract
Abstract A cache memory apparatus made up of a memory cell array (300) and a match detection circuit is disclosed. The match detection circuit produces a detection signal related to whether a search data coincides with a data read out of the memory cell array (300). The match detection circuit applies complementary signals (d, d) of the data read from the memory cell array (300) to the bases of bipolar differential transistors (10, 11), the gates of a pair of field effect transistors (16, 17) are supplied with complementary signals (a, a) of the search data, and the bases of a pair of emitter-follower transistors (12, 13) are connected to the collectors of the bipolar differential transistors (10, 11), thereby producing a detection signal (HITO) from the jointly-connected emitters thereof.
Inventors
- 👤 Makoto Suzuki
- 👤 Suguru Tachibana
- 👤 Hisayuki Higuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:52
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F12/0802; G06F12/0893; G06F12/0895; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
151 words
A cache memory apparatus comprising: a memory cell array; and a match detection circuit for producing a detection signal related to the judgement as to whether search data matches data read out of the memory cell array, wherein the match detection circuit includes: bipolar differential transistors in which the bases thereof are supplied with complementary signals of the data read out of the memory cell array and in which each has an emitter thereof connected to a first current source, a pair of field effect transistors in which the gates thereof are supplied with a complementary signal of the search data and the drains thereof are connected to the collectors of the bipolar differential transistors, respectively, and a pair of emitter-follower transistors in which the bases thereof are connected to the collectors of the bipolar differential transistors, respectively, and in which emitters thereof are jointly-connected for providing a detection output signal.
Claim 2
Dependent Claim
151 words
A cache memory apparatus comprising: a memory cell array; and a match detection circuit for producing a detection signal related to the judgement as to whether search data matches data read out of the memory cell array, wherein the match detection circuit includes: bipolar differential transistors in which the bases thereof are supplied with complementary signals of the data read out of the memory cell array and in which each has an emitter thereof connected to a first current source, a pair of field effect transistors in which the gates thereof are supplied with a complementary signal of the search data and the drains thereof are connected to the collectors of the bipolar differential transistors, respectively, and a pair of emitter-follower transistors in which the bases thereof are connected to the collectors of the bipolar differential transistors, respectively, and in which emitters thereof are jointly-connected for providing a detection output signal.
Claim 3
Dependent Claim
64 words
A cache memory apparatus according to claim 1, wherein each of the bipolar differential transistors is a multi-emitter type transistor having at least first and second emitters, the first emitters of the bipolar differential transistors of multi-emitter type are jointly connected to the first current source, and the second emitters of the bipolar differential transistor are connected to second and third current sources respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |