Protection of analog reference and bias voltage inputs

Claim 1

A protection circuit for connection between an input power providing terminal of a power supply and a power terminal of a CMOS integrated circuit having a parasitic latch device, comprising a first field effect transistor having its source-drain circuit connected between said input terminal and said power terminal, and its gate connected to a voltage supply terminal, the polarity of the voltage supply terminal being positive in the event the field effect transistor is of n-channel type and negative in the event the field effect transistor is of p-channel type whereby its source-drain circuit is biased on during normal supply of current from said input terminal to said power terminal, and wherein the polarity of an overvoltage appearing at said input terminal which is in the same polarity sense as the voltage supply biases said field effect transistor into its non-conducting state, thereby safeguarding the CMOS integrated circuit from currents resulting from the overvoltage, and a second field effect transistor having opposite channel type to said one field effect transistor having its source-drain circuit connected in series with the source-drain circuit of said one field effect transistor, and its gate connected to a voltage supply terminal having opposite polarity to that of the voltage supply terminal of said one field effect transistor wherein the polarity of an undervoltage appearing at said input terminal which is in the opposite polarity sense as said voltage terminal biases said second field effect transistor into its non-conducting state, thereby safeguarding the CMOS integrated circuit from currents resulting from the undervoltage.