US5218227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of manufacturing same
Assignee: Renesas Electronics Corp
•
Filing: 1991-09-24
•
Granted: 1993-06-08
•
Expires: 2011-09-24
Abstract
Abstract An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n + type buried layer (2a) lying in the lower part of an NPN transistor (100). A p + type buried layer (4a) is formed thick on the n type buried layer (2b) and insulated from the n + type buried layer (2a) by an isolation trench (7). A breakdown voltage at a junction of the p + type buried layer (4a) and the n type buried layer (2b) can be improved and, accordingly, the breakdown voltage of the whole device being improved. Low-controlled collector resistance of the PNP transistor (101a) prevents an amplification factor from decreasing.
Inventors
- 👤 Yasushi Kinoshita
- 👤 Kazuhito Niwano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:40
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D84/00; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/67; H10D84/673; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; H10W10/10; H10W10/17; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
177 words
A complementary bipolar transistor comprising: a p - type silicon substrate; an n type first buried layer of relatively large thickness having an impurity concentration in the order of 10 16 cm -3 , and an n + type second buried layer of relatively small thickness, said first and second buried layers being deposited complementarily to each other on one major surface of said substrate; a p + type third buried layer, having an impurity concentration in the order of 10 17 to 10 18 cm -3 , formed on said first buried layer; an n - type impurity region formed on said first and third buried layers and on said second buried layer; an insulative trench extending from the surface of said impurity region through to the vicinity of said substrate for dividing said impurity region into a first active region including said third buried layer and a second active region other than the first active region; a PNP transistor formed in said first active region; and an NPN transistor formed in said second active region.
Claim 2
Dependent Claim
177 words
A complementary bipolar transistor comprising: a p - type silicon substrate; an n type first buried layer of relatively large thickness having an impurity concentration in the order of 10 16 cm -3 , and an n + type second buried layer of relatively small thickness, said first and second buried layers being deposited complementarily to each other on one major surface of said substrate; a p + type third buried layer, having an impurity concentration in the order of 10 17 to 10 18 cm -3 , formed on said first buried layer; an n - type impurity region formed on said first and third buried layers and on said second buried layer; an insulative trench extending from the surface of said impurity region through to the vicinity of said substrate for dividing said impurity region into a first active region including said third buried layer and a second active region other than the first active region; a PNP transistor formed in said first active region; and an NPN transistor formed in said second active region.
Claim 3
Dependent Claim
37 words
A complementary bipolar transistor according to claim 1, wherein: said insulative trench prevents said second buried layer from infringing upon said first active region, and prevents said first buried layer from infringing upon said second active region.
Claim 4
Dependent Claim
176 words
A complementary bipolar transistor comprising: a p - silicon substrate; an n type first buried layer of relatively large thickness having an impurity concentration in the order of 10 16 cm -3 , and an n + type second buried layer of relatively small thickness, said first and second buried layers being deposited complementarily to each other on one major surface of said substrate; a p + third buried layer, having an impurity concentration in the order of 10 17 to 10 18 cm -3 , formed on said first buried layer; an n - type impurity region formed on said first and third buried layers and on said second buried layer; an insulative trench means extending from the surface of said impurity region through to the vicinity of said substrate for dividing said impurity region into a first active region including said third buried layer and a second active region other than the first active region; a PNP transistor formed in said first active region; and an NPN transistor formed in said second active region.
Claim 5
Dependent Claim
176 words
A complementary bipolar transistor comprising: a p - silicon substrate; an n type first buried layer of relatively large thickness having an impurity concentration in the order of 10 16 cm -3 , and an n + type second buried layer of relatively small thickness, said first and second buried layers being deposited complementarily to each other on one major surface of said substrate; a p + third buried layer, having an impurity concentration in the order of 10 17 to 10 18 cm -3 , formed on said first buried layer; an n - type impurity region formed on said first and third buried layers and on said second buried layer; an insulative trench means extending from the surface of said impurity region through to the vicinity of said substrate for dividing said impurity region into a first active region including said third buried layer and a second active region other than the first active region; a PNP transistor formed in said first active region; and an NPN transistor formed in said second active region.
Claim 6
Dependent Claim
39 words
A complementary bipolar transistor according to claim 3, wherein: said insulative trench means is for preventing said second layer from infringing upon said first active region, and preventing said first buried layer from infringing upon said second active region.
References Cited (Backward Citations)
US4898836A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |