Absolute value arithmetic circuit

Claim 2

An absolute value arithmetic circuit for computing an absolute value of a difference between two binary input signals, comprising: a computing circuit for computing a difference between said two input signals and generating a first signal; a ones complementor for non-inverting or inverting said first signal from said computing circuit in accordance with a sign bit of said first signal to generate a second signal; a priority encoder coupled to receive said second signal for searching said second signal for the position of the first "0" bit from the least significant digit bit of said second signal and for delivering an encoder signal indicating the position of the first "0" bit; and a bit inverting circuit coupled to receive the second signal and the encoder signal for inverting and outputting bits from the least significant digit bit to said "0" bit position of the second signal in accordance with said encoder signal, and for outputting bits from a bit higher than said first "0" bit to the most significant digit bit of the second signal without inverting the bits.

Claim 3

An absolute value arithmetic circuit as set forth in claim 1 wherein said computing circuit is a subtractor.

Claim 4

An absolute value arithmetic circuit as set forth in claim 1 wherein said computing circuit is an arithmetic logic unit.

Claim 5

An absolute value arithmetic circuit for computing the difference between a first binary input signal and a second binary input signal, comprising: a calculating circuit for calculating the difference between the first binary input signal and second binary input signal and outputting a first, n-bit, binary output signal having first through n-th bits corresponding to the difference, wherein n is a natural number; a complementary circuit coupled to receive the first, n-bit binary output signal for outputting a second, n-bit, binary output signal, wherein said second, n-bit, binary output signal is the ones complement of the first, n-bit, binary output signal when the first bit of the first, n-bit, binary output signal is in a first state and for outputting a second, n-bit, binary output signal equal to the first, n-bit, binary output signal when the first bit is in a second state; an encoder coupled to receive the second, n-bit, binary output signal and to detect an i-th bit thereof for outputting a position signal indicating the position of the i-th bit, wherein the i-th bit is in the second state and the i+1th to n-th bits are in the first state, and wherein i is a natural number not greater than n; and an inverting circuit coupled to receive the second, n-bit, binary output signal and the position signal for providing the ones complement of the i-th bit to the n-th bit of the second, n-bit, binary output signal and for outputting a third, n-bit, binary signal, representing the absolute value of the difference between the first and second binary input signals.

Claim 6

An absolute value arithmetic circuit for computing the difference between a first binary input signal and a second binary input signal, comprising: a calculating circuit for calculating the difference between the first binary input signal and second binary input signal and outputting a first, n-bit, binary output signal having first through n-th bits corresponding to the difference, wherein n is a natural number; a complementary circuit coupled to receive the first, n-bit binary output signal for outputting a second, n-bit, binary output signal, wherein said second, n-bit, binary output signal is the ones complement of the first, n-bit, binary output signal when the first bit of the first, n-bit, binary output signal is in a first state and for outputting a second, n-bit, binary output signal equal to the first, n-bit, binary output signal when the first bit is in a second state; an encoder coupled to receive the second, n-bit, binary output signal and to detect an i-th bit thereof for outputting a position signal indicating the position of the i-th bit, wherein the i-th bit is in the second state and the i+1th to n-th bits are in the first state, and wherein i is a natural number not greater than n; and an inverting circuit coupled to receive the second, n-bit, binary output signal and the position signal for providing the ones complement of the i-th bit to the n-th bit of the second, n-bit, binary output signal and for outputting a third, n-bit, binary signal, representing the absolute value of the difference between the first and second binary input signals.

Claim 7

An absolute value arithmetic circuit according to claim 4 wherein the first bit is the most significant bit (MSB) and the n-th bit is the least significant bit (LSB).