Patent US5216391A successfully refreshed from Google Patents.
US5216391A
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MSK modulator having a digital quadrature reference waveform generator
Assignee: Kenwood KK
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Filing: 1992-04-22
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Granted: 1993-06-01
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Expires: 2012-04-22
Abstract
Abstract An MSK modulator providing a high precision digital phase adjustment with a simple circuit structure. A sample data of a sine wave or cosine wave is read from a memory at an address calculated from an initial address value. The initial address value is set in accordance with the amount of phase to be adjusted. A predetermined number of sample data read from the memory is held, outputted in a predetermined order, and converted into an analog signal. The phase of the converted analog signal is adjusted, and thereafter multiplied by an input baseband signal. The multiplied result is outputted as a modulation signal.
Inventors
- 👤 Kenichi Shiraishi
- 👤 Souichi Shinjo
- 👤 Shunichi Tada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:50
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2003; H04L27/2007; H04L27/2014
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
42 words
An MSK modulator performing a process of multiplying a dibit baseband signal by a reference wave signal obtained from a clock signal having a symbol rate, comprising a digital reference wave generator for generating in a digital manner said reference wave signal.
Claim 2
Dependent Claim
42 words
An MSK modulator performing a process of multiplying a dibit baseband signal by a reference wave signal obtained from a clock signal having a symbol rate, comprising a digital reference wave generator for generating in a digital manner said reference wave signal.
Claim 3
Dependent Claim
51 words
An MSK modulator according to claim 1, wherein said digital reference wave generator generates reference wave data in accordance with over-sample data, converts said generated reference wave data into an analog signal at a D/A converter, and outputs said analog signal passed through a low-pass filter as said reference wave signal.
Claim 4
Dependent Claim
48 words
An MSK modulator according to claim 2, further comprising a plurality of fixed data memories for storing fixed values to be inputted to tri-state buffers, said tri-state buffers selecting desired data from said plurality of fixed data memories and outputting said selected desired data to said D/A converter.
Claim 5
Dependent Claim
139 words
An MSK modulator having a digital phase adjusting circuit, said digital phase adjusting circuit comprising: a memory for storing sample data of one of a sine wave and a cosine wave; an initial value setting circuit for setting an initial address value of said memory; a read circuit for outputting a predetermined address signal to said memory in accordance with said initial address value from said initial value setting circuit; a waveform data circuit for holding a predetermined number of said sample data read from said memory and outputting said predetermined number of said sample data in a predetermined order; a converter circuit for converting said data from said waveform data circuit into an analog signal; and a multiplier circuit for multiplying an output signal from said converter circuit by an input baseband signal and outputting the multiplied result.
Claim 6
Dependent Claim
139 words
An MSK modulator having a digital phase adjusting circuit, said digital phase adjusting circuit comprising: a memory for storing sample data of one of a sine wave and a cosine wave; an initial value setting circuit for setting an initial address value of said memory; a read circuit for outputting a predetermined address signal to said memory in accordance with said initial address value from said initial value setting circuit; a waveform data circuit for holding a predetermined number of said sample data read from said memory and outputting said predetermined number of said sample data in a predetermined order; a converter circuit for converting said data from said waveform data circuit into an analog signal; and a multiplier circuit for multiplying an output signal from said converter circuit by an input baseband signal and outputting the multiplied result.
References Cited (Backward Citations)
US5022054A
Cited
US4897620A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |